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公开(公告)号：US5761521A
公开(公告)日：1998-06-02
申请号：US619496
申请日：1996-03-26
CPC分类号： G06F7/026
摘要： A processor for character strings A, B of variable length serves for the fast detection of match, mismatch and comparative difference conditions between them. The character strings, whose lengths are delimited by character string termination marks, are split into consecutive substrings with a byte count corresponding to the data path width, and processed to detect a match, a mismatch and an end-of-byte mark. Each substring is routed via operand registers (16,18) in parallel to an arithmetic unit (20), a logic unit (22) and a comparator unit (24) and simultaneously processed. The arithmetic unit (20) subtracts one substring from the other substring, the logic unit (22) compares both substrings with each other and the comparator unit (24) compares the bytes of both substrings with the contents of a marking register (26), previously set to the end-of-string mark. These operations are executed in one machine cycle. Output signals from the comparator unit serve to indicate the equality of both substrings, output signals from the logic unit serve to indicate the inequality of both substrings and a carry signal from the arithmetic unit serves at the same time to indicate which of the two substrings is the greater or the lesser.
摘要翻译： PCT No.PCT / EP94 / 03045 Sec。 371日期：1996年3月26日 102（e）1996年3月26日PCT PCT 1994年9月12日PCT公布。 WO95 / 10803 PCT出版物 日期1995年04月20日可变长度的字符串A，B的处理器用于快速检测它们之间的匹配，不匹配和比较差异条件。 长度由字符串终止符分隔的字符串被分割成与数据路径宽度相对应的字节数的连续子字符串，并被处理以检测匹配，不匹配和字节结尾标记。 每个子串通过操作数寄存器（16,18）并行地运算到运算单元（20），逻辑单元（22）和比较器单元（24）并同时处理。 算术单元（20）从另一个子串中减去一个子串，逻辑单元（22）将两个子串彼此进行比较，比较单元（24）将两个子串的字节与标记寄存器（26）的内容进行比较， 以前设置为字符串结束标记。 这些操作在一个机器周期中执行。 来自比较器单元的输出信号用于指示两个子串的相等，来自逻辑单元的输出信号用于指示两个子串的不等式，并且来自算术单元的进位信号同时工作以指示两个子串中的哪一个是 越来越大。
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2.发明授权Hierarchical memory system for microcode and means for correcting errors in the microcode 失效用于微码的分层存储器系统和用于校正微代码中的错误的装置
公开(公告)号：US5898867A
公开(公告)日：1999-04-27
申请号：US132410
申请日：1993-10-06
CPC分类号： G06F9/268 , G06F11/1028 , G06F11/141 , G06F9/24 , G06F9/26 , G06F9/328 , G06F11/1008
摘要： A multiprocessor computer system includes a system clock, a main memory connected through a memory bus to a microinstruction memory and a microinstruction decoder. Circuitry detects whether the microinstruction being decoded is the wrong microinstruction or has a parity error. On detection of such an erroneous microinstruction, the microinstruction is reloaded from the main memory into the microinstruction memory and then passed to the microinstruction decoder without interrupting the system clock or operation of the other processors.
摘要翻译： 多处理器计算机系统包括系统时钟，通过存储器总线连接到微指令存储器的主存储器和微指令解码器。 电路检测是否正在解码的微指令是错误的微指令还是具有奇偶校验错误。 在检测到这种错误的微指令时，微指令从主存储器重新加载到微指令存储器中，然后传递到微指令解码器，而不中断其他处理器的系统时钟或操作。
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