公开(公告)号：US20060108622A1

公开(公告)日：2006-05-25

申请号：US11248629

申请日：2005-10-12

申请人： Heung-jin Joo ,  Ki-nam Kim ,  Yoon-jong Song

发明人： Heung-jin Joo ,  Ki-nam Kim ,  Yoon-jong Song

IPC分类号： H01L29/94 ,  H01L21/00

CPC分类号： H01L28/55 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/57

摘要： Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.

公开(公告)号：US07348616B2

公开(公告)日：2008-03-25

申请号：US11248629

申请日：2005-10-12

申请人： Heung-jin Joo ,  Ki-nam Kim ,  Yoon-jong Song

发明人： Heung-jin Joo ,  Ki-nam Kim ,  Yoon-jong Song

IPC分类号： H01L29/76

CPC分类号： H01L28/55 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/57

摘要： Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.

摘要翻译： 诸如存储器件的铁电集成电路器件形成在集成电路衬底上。 铁电电容器在集成电路衬底上，并且集成电路衬底上的另一结构覆盖至少一部分铁电电容器。 所述另外的结构包括至少一层，以提供对所述铁电电容器的氧气流的阻挡。 与强电介质电容器接触的氧气穿透路径介于铁电电容器和另外的结构之间。 提供氧流阻挡的层可以是封装的阻挡层。 还提供了用于形成诸如存储器件的铁电集成电路器件的方法。

公开(公告)号：US06979881B2

公开(公告)日：2005-12-27

申请号：US10308843

申请日：2002-12-03

申请人： Heung-jin Joo ,  Ki-nam Kim ,  Yoon-jong Song

发明人： Heung-jin Joo ,  Ki-nam Kim ,  Yoon-jong Song

IPC分类号： H01L27/105 ,  H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/92

CPC分类号： H01L28/55 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/57

摘要： Ferroelectric integrated circuit devices, such as memory devices, are formed on an integrated circuit substrate. Ferroelectric capacitor(s) are on the integrated circuit substrate and a further structure on the integrated circuit substrate overlies at least a part of the Ferroelectric capacitor(s). The further structure includes at least one layer providing a barrier to oxygen flow to the ferroelectric capacitor(s). An oxygen penetration path contacting the ferroelectric capacitor(s) is interposed between the ferroelectric capacitor(s) and the further structure. The layer providing a barrier to oxygen flow may be an encapsulated barrier layer. Methods for forming ferroelectric integrated circuit devices, such as memory devices, are also provided.

摘要翻译： 诸如存储器件的铁电集成电路器件形成在集成电路衬底上。 铁电电容器在集成电路基板上，并且集成电路基板上的另外的结构覆盖在铁电电容器的至少一部分上。 所述另外的结构包括至少一层，以提供对所述铁电电容器的氧气流的阻挡。 与强电介质电容器接触的氧气穿透路径介于铁电电容器和另外的结构之间。 提供氧流阻挡的层可以是封装的阻挡层。 还提供了用于形成诸如存储器件的铁电集成电路器件的方法。

公开(公告)号：US07479405B2

公开(公告)日：2009-01-20

申请号：US11982940

申请日：2007-11-06

申请人： Jae-hyun Park ,  Hyeong-geun An ,  Su-jin Ahn ,  Yoon-jong Song ,  Hyung-joo Youn ,  Kyu-chul Kim

发明人： Jae-hyun Park ,  Hyeong-geun An ,  Su-jin Ahn ,  Yoon-jong Song ,  Hyung-joo Youn ,  Kyu-chul Kim

IPC分类号： H01L21/00

CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/144

摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

摘要翻译： 提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。 在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。 在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。 其他半导体衬底分别限定其它有源区。 在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。