公开(公告)号：US20180285003A1

公开(公告)日：2018-10-04

申请号：US15471166

申请日：2017-03-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Alexander Leslie Richardson ,  Moritz Josef Hoffmann ,  Dejan S. Milojicic

IPC: G06F3/06 ,  G06F9/52

Abstract: An example computing system may include a plurality of processors, persistent memory that is shared by the plurality of processors, and a memory-side accelerator that is to control access to the memory. A requesting processor of the plurality of processors may simultaneously request locking of and access to a target data object of the persistent memory by sending a single lock-and-access message to the memory-side accelerator. The lock-and-access message may include a first memory capability pointing to the target data object, a second memory capability pointing to a lock object that controls locking of the target data object, and a specified access operation that is requested. The memory-side accelerator may, in response to receiving the lock-and-access message: fetch locking information that is stored in the lock object pointed to by the second memory capability, and determine, based on the locking information, whether to lock and perform the requested access operation on the target data object pointed to by the first memory capability for the requesting processor.

公开(公告)号：US20190095356A1

公开(公告)日：2019-03-28

申请号：US15718214

申请日：2017-09-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S. Milojicic ,  Moritz Josef Hoffmann ,  Alexander Richardson ,  Qiong Cai

IPC: G06F12/14 ,  G06F12/121 ,  G06F12/02

CPC classification number: G06F12/1441 ,  G06F12/023 ,  G06F12/121 ,  G06F2212/1052 ,  G06F2212/621

Abstract: In one example, a processor sends a memory access request including a data capability and a handle which references a master capability. In response to receiving the memory access request, a memory controller checks whether the handle references a valid master capability and checks whether the data capability is within a scope of the master capability. In response to determining that the master capability is valid and the data capability is within the scope of the master capability, the memory controller returns a result of the memory access request to the processor.

公开(公告)号：US10387335B2

公开(公告)日：2019-08-20

申请号：US15718214

申请日：2017-09-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S. Milojicic ,  Moritz Josef Hoffmann ,  Alexander Richardson ,  Qiong Cai

IPC: G06F12/00 ,  G06F12/14 ,  G06F12/121 ,  G06F12/02

Abstract: In one example, a processor sends a memory access request including a data capability and a handle which references a master capability. In response to receiving the memory access request, a memory controller checks whether the handle references a valid master capability and checks whether the data capability is within a scope of the master capability. In response to determining that the master capability is valid and the data capability is within the scope of the master capability, the memory controller returns a result of the memory access request to the processor.