公开(公告)号：US10387335B2

公开(公告)日：2019-08-20

申请号：US15718214

申请日：2017-09-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S. Milojicic ,  Moritz Josef Hoffmann ,  Alexander Richardson ,  Qiong Cai

IPC: G06F12/00 ,  G06F12/14 ,  G06F12/121 ,  G06F12/02

Abstract: In one example, a processor sends a memory access request including a data capability and a handle which references a master capability. In response to receiving the memory access request, a memory controller checks whether the handle references a valid master capability and checks whether the data capability is within a scope of the master capability. In response to determining that the master capability is valid and the data capability is within the scope of the master capability, the memory controller returns a result of the memory access request to the processor.

公开(公告)号：US20180365158A1

公开(公告)日：2018-12-20

申请号：US15625631

申请日：2017-06-16

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dejan S. Milojicic ,  Moritz J. Hoffmann ,  Alexander Richardson

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F2212/1008

Abstract: In one example in accordance with the present disclosure, a system may comprise a memory accessor to access a memory and a pointer loader to load a virtual address (VA) pointer corresponding to a first location in the memory and a physical address (PA) pointer corresponding to the VA pointer. The system may comprise a pointer handler to determine a first physical address in the memory mapped to the first location in the memory and a location matcher to determine whether the second physical address mapped to the PA pointer matches the first physical address. The system may also comprise an exception handler to raise an exception when the second physical address does not match the first physical address.

公开(公告)号：US10303615B2

公开(公告)日：2019-05-28

申请号：US15625631

申请日：2017-06-16

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dejan S. Milojicic ,  Moritz J. Hoffmann ,  Alexander Richardson

IPC: G06F12/10

Abstract: In one example in accordance with the present disclosure, a system may comprise a memory accessor to access a memory and a pointer loader to load a virtual address (VA) pointer corresponding to a first location in the memory and a physical address (PA) pointer corresponding to the VA pointer. The system may comprise a pointer handler to determine a first physical address in the memory mapped to the first location in the memory and a location matcher to determine whether the second physical address mapped to the PA pointer matches the first physical address. The system may also comprise an exception handler to raise an exception when the second physical address does not match the first physical address.

公开(公告)号：US20190095356A1

公开(公告)日：2019-03-28

申请号：US15718214

申请日：2017-09-28

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Dejan S. Milojicic ,  Moritz Josef Hoffmann ,  Alexander Richardson ,  Qiong Cai

IPC: G06F12/14 ,  G06F12/121 ,  G06F12/02

CPC classification number: G06F12/1441 ,  G06F12/023 ,  G06F12/121 ,  G06F2212/1052 ,  G06F2212/621

Abstract: In one example, a processor sends a memory access request including a data capability and a handle which references a master capability. In response to receiving the memory access request, a memory controller checks whether the handle references a valid master capability and checks whether the data capability is within a scope of the master capability. In response to determining that the master capability is valid and the data capability is within the scope of the master capability, the memory controller returns a result of the memory access request to the processor.

公开(公告)号：US20180307623A1

公开(公告)日：2018-10-25

申请号：US15496228

申请日：2017-04-25

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Moritz J. Hoffmann ,  Alexander Richardson ,  Dejan S. Milojicic

IPC: G06F12/1045 ,  H04L9/32 ,  G06F12/14 ,  G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1054 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2212/65 ,  G06F2212/68 ,  H04L9/3247

Abstract: Examples disclosed herein relate to a memory controller interpreting capabilities returning datasets. A Central Processing Unit (CPU) is adapted to translate a first virtual address from a first capability to a first physical address, wherein the first capability is sent by a client application. The CPU is further adapted to send the first physical address to a memory controller coupled to a memory fabric. The memory controller loads a second capability located in the first physical address from the memory fabric, interprets an address encoded within the second capability as a second physical address, and returns a dataset located in the second physical address from the memory fabric.