公开(公告)号：US07911769B2

公开(公告)日：2011-03-22

申请号：US12487279

申请日：2009-06-18

申请人： Hideho Yamamura ,  Naoki Maru ,  Kazunori Nakajima ,  Koji Nisisu ,  Shigeo Oomae

发明人： Hideho Yamamura ,  Naoki Maru ,  Kazunori Nakajima ,  Koji Nisisu ,  Shigeo Oomae

IPC分类号： H02B1/20

CPC分类号： H05K1/0263 ,  H05K2201/10272

摘要： This invention prevents a deterioration of efficiency of a power supply apparatus due to a semiconductor power supply voltage drop, prevents an increase in wasted power, and prevents erroneous operations due to feeder wire voltage drop. In the mounting structure of electronic circuits having a plurality of busbars as current paths on a printed circuit board, the plurality of busbars have almost parallel portions spaced a predetermined distance apart; a span of the parallel portions of the plurality of busbars is greater than the predetermined distance; and in the parallel portions of the plurality of busbars, the plurality of busbars are connected by a wiring pattern. In the switching power supply apparatus built on a printed circuit board, with its output voltage of less than 2 V and its output current of more than 100 A, a means is provided for making the power efficiency higher than 70%.

摘要翻译： 本发明可防止由于半导体电源电压下降导致的电源装置的效率的劣化，防止浪费电力的增加，并且防止由于馈线电压下降引起的错误操作。 在具有作为印刷电路板上的电流路径的多个母线的电子电路的安装结构中，多个母线具有间隔开预定距离的几乎平行的部分; 多个汇流条的平行部分的跨度大于预定距离; 并且在多个母线的平行部分中，多个母线通过布线图案连接。 在内置于印刷电路板上的开关电源装置中，其输出电压小于2V，其输出电流大于100A，提供了使功率效率高于70％的装置。

公开(公告)号：US07548411B2

公开(公告)日：2009-06-16

申请号：US11260210

申请日：2005-10-28

申请人： Hideho Yamamura ,  Naoki Maru ,  Kazunori Nakajima ,  Koji Nisisu ,  Shigeo Oomae

发明人： Hideho Yamamura ,  Naoki Maru ,  Kazunori Nakajima ,  Koji Nisisu ,  Shigeo Oomae

IPC分类号： H02B1/20

CPC分类号： H05K1/0263 ,  H05K2201/10272

摘要： This invention prevents a deterioration of efficiency of a power supply apparatus due to a semiconductor power supply voltage drop, prevents an increase in wasted power, and prevents erroneous operations due to feeder wire voltage drop.In the mounting structure of electronic circuits having a plurality of busbars as current paths on a printed circuit board, the plurality of busbars have almost parallel portions spaced a predetermined distance apart; a span of the parallel portions of the plurality of busbars is greater than the predetermined distance; and in the parallel portions of the plurality of busbars, the plurality of busbars are connected by a wiring pattern. In the switching power supply apparatus built on a printed circuit board, with its output voltage of less than 2 V and its output current of more than 100 A, a means is provided for making the power efficiency higher than 70%.

摘要翻译： 本发明可防止由于半导体电源电压下降导致的电源装置的效率的劣化，防止浪费电力的增加，并且防止由于馈线电压下降引起的错误操作。 在具有作为印刷电路板上的电流路径的多个母线的电子电路的安装结构中，多个母线具有间隔开预定距离的几乎平行的部分; 多个汇流条的平行部分的跨度大于预定距离; 并且在多个母线的平行部分中，多个母线通过布线图案连接。 在内置于印刷电路板上的开关电源装置中，其输出电压小于2V，其输出电流大于100A，提供了使功率效率高于70％的装置。

公开(公告)号：US20090257210A1

公开(公告)日：2009-10-15

申请号：US12487279

申请日：2009-06-18

申请人： Hideho Yamamura ,  Naoki Maru ,  Kazunori Nakajima ,  Koji Nisisu ,  Shigeo Oomae

发明人： Hideho Yamamura ,  Naoki Maru ,  Kazunori Nakajima ,  Koji Nisisu ,  Shigeo Oomae

IPC分类号： H05K7/06

CPC分类号： H05K1/0263 ,  H05K2201/10272

摘要： This invention prevents a deterioration of efficiency of a power supply apparatus due to a semiconductor power supply voltage drop, prevents an increase in wasted power, and prevents erroneous operations due to feeder wire voltage drop. In the mounting structure of electronic circuits having a plurality of busbars as current paths on a printed circuit board, the plurality of busbars have almost parallel portions spaced a predetermined distance apart; a span of the parallel portions of the plurality of busbars is greater than the predetermined distance; and in the parallel portions of the plurality of busbars, the plurality of busbars are connected by a wiring pattern. In the switching power supply apparatus built on a printed circuit board, with its output voltage of less than 2 V and its output current of more than 100 A, a means is provided for making the power efficiency higher than 70%.

摘要翻译： 本发明可防止由于半导体电源电压下降导致的电源装置的效率的劣化，防止浪费电力的增加，并且防止由于馈线电压下降引起的错误操作。 在具有作为印刷电路板上的电流路径的多个母线的电子电路的安装结构中，多个母线具有间隔开预定距离的几乎平行的部分; 多个汇流条的平行部分的跨度大于预定距离; 并且在多个母线的平行部分中，多个母线通过布线图案连接。 在内置于印刷电路板上的开关电源装置中，其输出电压小于2V，其输出电流大于100A，提供了使功率效率高于70％的装置。

公开(公告)号：US20060092599A1

公开(公告)日：2006-05-04

申请号：US11260210

申请日：2005-10-28

申请人： Hideho Yamamura ,  Naoki Maru ,  Kazunori Nakajima ,  Koji Nisisu ,  Shigeo Oomae

发明人： Hideho Yamamura ,  Naoki Maru ,  Kazunori Nakajima ,  Koji Nisisu ,  Shigeo Oomae

IPC分类号： H02B1/20

CPC分类号： H05K1/0263 ,  H05K2201/10272

摘要： This invention prevents a deterioration of efficiency of a power supply apparatus due to a semiconductor power supply voltage drop, prevents an increase in wasted power, and prevents erroneous operations due to feeder wire voltage drop. In the mounting structure of electronic circuits having a plurality of busbars as current paths on a printed circuit board, the plurality of busbars have almost parallel portions spaced a predetermined distance apart; a span of the parallel portions of the plurality of busbars is greater than the predetermined distance; and in the parallel portions of the plurality of busbars, the plurality of busbars are connected by a wiring pattern. In the switching power supply apparatus built on a printed circuit board, with its output voltage of less than 2 V and its output current of more than 100 A, a means is provided for making the power efficiency higher than 70%.

公开(公告)号：US07208883B2

公开(公告)日：2007-04-24

申请号：US11293212

申请日：2005-12-05

申请人： Naoki Maru ,  Hideho Yamamura ,  Koji Nisisu ,  Shigeo Oomae

发明人： Naoki Maru ,  Hideho Yamamura ,  Koji Nisisu ,  Shigeo Oomae

IPC分类号： H05B37/02

CPC分类号： H02M3/33592 ,  H02M1/32 ,  H02M2001/0009 ,  Y02B70/1475

摘要： In the current detection circuit that detects the output currents of a switching power supply circuit, an improved current detection circuit makes it possible to detect the output current directions of power supplies solves the malfunction of the power supplies vibrating or diverging during changes in load state and during parallel operation, and thus implements stable operation. The direction of an output current I2 can be detected by using the current detection circuit 8 that has multiple switching elements S1 to S4 each operating synchronously with an inverter circuit.

摘要翻译： 在检测开关电源电路的输出电流的电流检测电路中，改进的电流检测电路能够检测电源的输出电流方向，解决了在负载状态的变化期间振动或发散的电源的故障，以及 并联运行时，可实现稳定运行。 可以通过使用具有与逆变器电路同步操作的多个开关元件S1〜S4的电流检测电路8来检测输出电流I 2的方向。

公开(公告)号：US20060132062A1

公开(公告)日：2006-06-22

申请号：US11293212

申请日：2005-12-05

申请人： Naoki Maru ,  Hideho Yamamura ,  Koji Nisisu ,  Shigeo Oomae

发明人： Naoki Maru ,  Hideho Yamamura ,  Koji Nisisu ,  Shigeo Oomae

IPC分类号： H05B37/02

CPC分类号： H02M3/33592 ,  H02M1/32 ,  H02M2001/0009 ,  Y02B70/1475

摘要： In the current detection circuit that detects the output currents of a switching power supply circuit, an improved current detection circuit makes it possible to detect the output current directions of power supplies solves the malfunction of the power supplies vibrating or diverging during changes in load state and during parallel operation, and thus implements stable operation. The direction of an output current I2 can be detected by using the current detection circuit 8 that has multiple switching elements S1 to S4 each operating synchronously with an inverter circuit.

摘要翻译： 在检测开关电源电路的输出电流的电流检测电路中，改进的电流检测电路能够检测电源的输出电流方向，解决了在负载状态的变化期间振动或发散的电源的故障，以及 并联运行时，可实现稳定运行。 可以通过使用具有与逆变器电路同步操作的多个开关元件S1〜S4的电流检测电路8来检测输出电流I 2的方向。

公开(公告)号：US20050174190A1

公开(公告)日：2005-08-11

申请号：US10628234

申请日：2003-07-29

申请人： Masayoshi Yagyu ,  Tatsuya Saito ,  Shigeo Oomae ,  Mitsuo Akashi

发明人： Masayoshi Yagyu ,  Tatsuya Saito ,  Shigeo Oomae ,  Mitsuo Akashi

IPC分类号： H01P5/08

CPC分类号： H01P5/08

摘要： A connection structure is applied to mutually connect a first and a second transmission line that is planar in shape and that has a ground conductor on a second main surface, such as a microstrip line or a coplanar line with a ground. The first and the second transmission lines are superposed one upon the other, and their signal wiring patterns are electrically connected, as are their ground conductors. An end surface of the first transmission line is substantially covered by a conductor layer connected to the ground conductor. The connection structure can achieve good signal transmission characteristics up to high-frequency bands on the order of several tens of gigahertz.

摘要翻译： 应用连接结构来相互连接形状为平面的第一和第二传输线，并且在诸如微带线或与地面的共面线之类的第二主表面上具有接地导体。 第一和第二传输线彼此重叠，并且它们的信号布线图形与它们的接地导体一样电连接。 第一传输线的端面基本上被连接到接地导体的导体层覆盖。 连接结构可以达到高达几十千兆赫兹的高频带的良好的信号传输特性。

公开(公告)号：US07277643B2

公开(公告)日：2007-10-02

申请号：US10629755

申请日：2003-07-30

申请人： Takashige Baba ,  Tatsuya Saito ,  Masayoshi Yagyu ,  Shigeo Oomae

发明人： Takashige Baba ,  Tatsuya Saito ,  Masayoshi Yagyu ,  Shigeo Oomae

IPC分类号： H04B10/00 ,  H04L27/00 ,  H04L12/50 ,  H04J3/06

CPC分类号： H04L25/14 ,  H04L7/033

摘要： A signal communication apparatus of a clock reproduction system in which clock signals are extracted from each of parallel data signals for redigitizing each of the data signals. The apparatus includes a reference clock signal generating circuit which is comprised of a clock extraction circuit for extracting a clock signal from each of a plurality of bits of received data signals, and a clock signal selection circuit for selecting one of the extracted clock signals. Alternatively, the reference clock signal generating circuit may be comprised of a data signal selection circuit for selecting one of a plurality of received data signals, and a clock extraction circuit for extracting a clock signal from the selected bit. Based on the resultant reference clock signal, clock signals are obtained that are phase-adjusted for redigitizing each bit of the received data signals. The selection made in the selection circuit is switched on the basis of the output of a clock signal monitoring circuit that detects the occurrence of abnormalities in the frequency of the extracted clock signal. Thus, the extraction of clock can be continued using other bits in the event of an abnormality in the bit from which the clock is being extracted.

摘要翻译： 一种时钟再现系统的信号通信装置，其中从每个并行数据信号中提取时钟信号，以对每个数据信号进行重新排序。 该装置包括一个参考时钟信号产生电路，它包括一个时钟提取电路，用于从接收的数据信号的多个比特中提取一个时钟信号;以及时钟信号选择电路，用于选择所提取的时钟信号之一。 或者，参考时钟信号发生电路可以包括用于选择多个接收数据信号中的一个的数据信号选择电路和用于从所选位提取时钟信号的时钟提取电路。 基于所得到的参考时钟信号，获得相位调整的时钟信号，以对接收到的数据信号的每一位进行重新编码。 在选择电路中进行的选择是基于检测提取的时钟信号的频率异常的发生的时钟信号监视电路的输出而被切换的。 因此，在提取时钟的位的异常的情况下，可以使用其他位继续提取时钟。

公开(公告)号：US20060082422A1

公开(公告)日：2006-04-20

申请号：US11240455

申请日：2005-10-03

申请人： Masayoshi Yagyu ,  Tatsuya Saito ,  Shigeo Oomae ,  Mitsuo Akashi

发明人： Masayoshi Yagyu ,  Tatsuya Saito ,  Shigeo Oomae ,  Mitsuo Akashi

IPC分类号： H03H7/38

CPC分类号： H01P5/08

摘要： A connection structure is applied to mutually connect a first and a second transmission line that is planar in shape and that has a ground conductor on a second main surface, such as a microstrip line or a coplanar line with a ground. The first and the second transmission lines are superposed one upon the other, and their signal wiring patterns are electrically connected, as are their ground conductors. An end surface of the first transmission line is substantially covered by a conductor layer connected to the ground conductor. The connection structure can achieve good signal transmission characteristics up to high-frequency bands on the order of several tens of gigahertz.

摘要翻译： 应用连接结构来相互连接形状为平面的第一和第二传输线，并且在诸如微带线或与地面的共面线之类的第二主表面上具有接地导体。 第一和第二传输线彼此重叠，并且它们的信号布线图形与它们的接地导体一样电连接。 第一传输线的端面基本上被连接到接地导体的导体层覆盖。 连接结构可以达到高达几十千兆赫兹的高频带的良好的信号传输特性。