公开(公告)号：US6022772A

公开(公告)日：2000-02-08

申请号：US966543

申请日：1997-11-10

申请人： Hirohito Watanabe ,  Ichiroh Honma

发明人： Hirohito Watanabe ,  Ichiroh Honma

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L21/8234

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： In a semiconductor device, such as a memory cell, including a capacitor, a corrugated electrode is used as a lower electrode of the capacitor and is covered with an insulation film to be opposed to an upper electrode. The corrugated electrode is specified in section by a series of folded portions which are alternately folded vertically and horizontally. Practically, the corrugated electrode is formed by a corrugated wall which surrounds a hollow space and which has a rectangular or a polygonal shape on a plane. Alternatively, the corrugated wall has an irregular surface formed by an aggregation of grains so as to effectively widen a surface of the lower electrode. Such a corrugated electrode may be manufactured by a mold which is formed by selectively etching a stack of first-kind spacer films and second-kind spacer films.

摘要翻译： 在诸如包括电容器的存储单元的半导体器件中，使用波纹状电极作为电容器的下电极，并且被绝缘膜覆盖以与上电极相对。 波纹状电极通过垂直和水平交替折叠的一系列折叠部分来界定。 实际上，波纹状电极由围绕中空空间的波纹壁形成，并且在平面上具有矩形或多边形。 或者，波纹状壁具有由晶粒聚集形成的不规则表面，以有效地加宽下电极的表面。 这种波纹状电极可以通过通过选择性地蚀刻第一种间隔膜和第二种间隔膜的堆叠形成的模具来制造。

公开(公告)号：US5753949A

公开(公告)日：1998-05-19

申请号：US710939

申请日：1996-09-24

申请人： Ichiroh Honma ,  Hirohito Watanabe

发明人： Ichiroh Honma ,  Hirohito Watanabe

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： Used nearer to a MOS transistor (25, 29(1), 29(2)) together with another capacitor electrode (39) with a dielectric film (37) interposed for use in a DRAM, a capacitor electrode comprises a conductor pole (53) and a conductor layer (55) which is held by the conductor pole and comprises a plate portion (57) extended perpendicular to a pole axis and having a plate periphery and a peripheral portion (59) extended parallel to the pole axis from the plate periphery towards a pole end. Preferably, the conductor layer is held by the pole on a plurality of levels. A planar conductor layer may additionally be held at the pole end perpendicular to the pole axis. Word (41) and bit (49) lines are embedded in an insulator layer (43, 51) for the capacitor and the transistor.

摘要翻译： 与另一个电容器电极（39）一起更靠近MOS晶体管（25,29（1），29（2）），电容器电极插入用于DRAM中，电容器电极包括导体极（53 ）和导体层（55），所述导体层（55）由所述导体极保持，并且包括垂直于极轴延伸并具有板周边的平板部（57）和从所述平板平行于所述极轴延伸的周边部（59） 周边朝极端。 优选地，导体层由极保持在多个层上。 平面导体层可以另外保持在垂直于极轴的极端。 字（41）和位（49）线被嵌入用于电容器和晶体管的绝缘体层（43,41）中。

公开(公告)号：US5837594A

公开(公告)日：1998-11-17

申请号：US868582

申请日：1997-06-04

申请人： Ichiroh Honma ,  Hirohito Watanabe

发明人： Ichiroh Honma ,  Hirohito Watanabe

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/20

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： Used nearer to a MOS transistor (25, 29(1), 29(2)) together with another capacitor electrode (39) with a dielectric film (37) interposed for use in a DRAM, a capacitor electrode is manufactured to include a conductor pole (53) and a tray-shaped conductor layer (55) which is held by the conductor pole and to include a plate portion (57) extended perpendicular to a pole axis and having a plate periphery and a peripheral portion (59) extended parallel to the pole axis from the plate periphery towards a pole end. Preferably, the tray-shaped conductor layer is held by the pole on a plurality of levels. A planar conductor layer may additionally be held at the pole end perpendicular to the pole axis. Word (41) and bit (49) lines are embedded in an insulator layer (43, 51) for the capacitor and the transistor.

摘要翻译： 使用更接近于MOS晶体管（25,29（1），29（2））的电容器电极（39）和具有插入用于DRAM的电介质膜（37）的电容器电极（39），制造电容器电极以包括导体 （53）和由导体极保持的托盘状导体层（55），并且包括垂直于极轴延伸的板部（57），并且具有板周边和平行延伸的周边部分（59） 从极板周边向极端延伸到极轴。 优选地，托盘状导体层由极保持在多个级上。 平面导体层可以另外保持在垂直于极轴的极端。 字（41）和位（49）线被嵌入用于电容器和晶体管的绝缘体层（43,41）中。

公开(公告)号：US5835337A

公开(公告)日：1998-11-10

申请号：US723274

申请日：1996-09-30

申请人： Hirohito Watanabe ,  Ichiroh Honma

发明人： Hirohito Watanabe ,  Ichiroh Honma

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01G4/30

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： In a semiconductor device, such as a memory cell, including a capacitor, a corrugated electrode is used as a lower electrode of the capacitor and is covered with an insulation film to be opposed to an upper electrode. The corrugated electrode is specified in section by a series of folded portions which are alternately folded vertically and horizontally. Practically, the corrugated electrode is formed by a corrugated wall which surrounds a hollow space and which has a rectangular or a polygonal shape on a plane. Alternatively, the corrugated wall has an irregular surface formed by an aggregation of grains so as to effectively widen a surface of the lower electrode. Such a corrugated electrode may be manufactured by a mold which is formed by selectively etching a stack of first-kind spacer films and second-kind spacer films.