公开(公告)号：US5986915A

公开(公告)日：1999-11-16

申请号：US154734

申请日：1998-09-17

申请人： Hiromi Okimoto ,  Masanori Hayashikoshi ,  Youichi Tobita

发明人： Hiromi Okimoto ,  Masanori Hayashikoshi ,  Youichi Tobita

IPC分类号： G06F11/20 ,  G11C8/08 ,  G11C8/10 ,  G11C29/00 ,  G11C7/00

CPC分类号： G06F11/2007 ,  G11C29/70 ,  G11C29/78 ,  G11C29/832 ,  G11C8/08 ,  G11C8/10

摘要： A column select line includes a first layer column select line and a second layer column select line formed above the first layer column select line and connected thereto at any point. Furthermore, clamping circuits each for clamping each word line of paired main word lines at a constant potential are provided in a semiconductor memory device having main and secondary word line structure. With such a structure, malfunction due to multiselection of memory cells can be avoided even when the column select line or the paired main word lines is disconnected.

摘要翻译： 列选择线包括形成在第一层列选择线上方并在任何点连接的第一层列选择线和第二层列选择线。 此外，在具有主字线和次级字线结构的半导体存储器件中提供各自用于将一对主字线的每个字线固定为恒定电位的钳位电路。 利用这种结构，即使当列选择线或成对的主字线断开时，也可以避免由于存储器单元的多选而导致的故障。

公开(公告)号：US5825694A

公开(公告)日：1998-10-20

申请号：US807007

申请日：1997-02-26

申请人： Hiromi Okimoto ,  Masanori Hayashikoshi ,  Youichi Tobita

发明人： Hiromi Okimoto ,  Masanori Hayashikoshi ,  Youichi Tobita

IPC分类号： G06F11/20 ,  G11C8/08 ,  G11C8/10 ,  G11C29/00 ,  G11C7/00

CPC分类号： G06F11/2007 ,  G11C29/70 ,  G11C29/78 ,  G11C29/832 ,  G11C8/08 ,  G11C8/10

摘要： A column select line includes a first layer column select line and a second layer column select line formed above the first layer column select line and connected thereto at any point. Furthermore, clamping circuits each for clamping each word line of paired main word lines at a constant potential are provided in a semiconductor memory device having main and secondary word line structure. With such a structure, malfunction due to multiselection of memory cells can be avoided even when the column select line or the paired main word lines is disconnected.

公开(公告)号：US5835419A

公开(公告)日：1998-11-10

申请号：US807742

申请日：1997-02-27

申请人： Tooru Ichimura ,  Hiromi Okimoto ,  Masanori Hayashikoshi ,  Youichi Tobita

发明人： Tooru Ichimura ,  Hiromi Okimoto ,  Masanori Hayashikoshi ,  Youichi Tobita

IPC分类号： G06F11/20 ,  G11C7/12 ,  G11C8/08 ,  G11C8/10 ,  G11C29/00 ,  G11C16/04

CPC分类号： G06F11/2007 ,  G11C29/70 ,  G11C29/832 ,  G11C8/08 ,  G11C8/10

摘要： A semiconductor memory device includes: subarrays having memory cells each arranged at cross points of a plurality of bit lines and a plurality of word lines; a row decoder for selecting among the word lines; a column decoder for supplying a select signal to transfer gates for selecting among paired bit lines; and a clamping circuit for fixing the potential of a column select line at a constant potential before the column decoder is activated.

摘要翻译： 一种半导体存储器件包括：具有各自布置在多个位线和多个字线的交叉点处的存储器单元的子阵列; 用于在字线之间进行选择的行解码器; 列解码器，用于提供选择信号以传送门，以便在成对的位线之间进行选择; 以及用于在列解码器被激活之前将列选择线的电位固定为恒定电位的钳位电路。

公开(公告)号：US08194817B2

公开(公告)日：2012-06-05

申请号：US12951705

申请日：2010-11-22

申请人： Youichi Tobita ,  Isao Nojiri ,  Seiichiro Mori ,  Takashi Miyayama

发明人： Youichi Tobita ,  Isao Nojiri ,  Seiichiro Mori ,  Takashi Miyayama

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G09G2320/0233 ,  G11C19/184

摘要： A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit.

摘要翻译： 移位寄存器电路包括连接在时钟端子和输出端子之间的第一晶体管，用于响应于前一级的输出信号的激活而对第一晶体管的控制电极进行充电的第二晶体管，用于对控制器进行放电的第三晶体管 第一晶体管的电极，使用第三晶体管的控制电极作为输出端的反相器，以及在断电时对逆变器的输入端进行放电并在通电之后被截止的第四晶体管。 作为逆变器的负载元件的第五晶体管在通电时对第三晶体管的控制电极进行充电。 从而可以初始化节点的各个级别而没有任何外部初始化信号，并且防止移位寄存器电路中的输出信号的电平变化率的降低。

公开(公告)号：US08175216B2

公开(公告)日：2012-05-08

申请号：US12647108

申请日：2009-12-24

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G11C19/00

CPC分类号： G11C19/184 ,  G09G2310/0286 ,  G09G2330/021

摘要： A shift register circuit is provided that can decrease a power consumption caused by a clock signal and can achieve a high driving capacity. A unit shift register has a first transistor that activates an output signal when a power supply potential is provided to an output terminal. A pull-up driving circuit for driving the first transistor has a second transistor for providing a clock signal to a node connected to the gate of the first transistor and a boosting circuit for the node. When an output signal of a preceding stage is activated, the second transistor turns on. Thereafter, when the clock signal is activated, and the node is charged, the second transistor turns off. The boosting circuit increases the potential at the node when the second transistor turns off. Therefore, the first transistor can operate in non-saturation region and activate the output signal.

摘要翻译： 提供一种移位寄存器电路，其可以降低由时钟信号引起的功耗并且可以实现高的驱动能力。 单元移位寄存器具有第一晶体管，当向输出端子提供电源电位时，其激活输出信号。 用于驱动第一晶体管的上拉驱动电路具有第二晶体管，用于向连接到第一晶体管的栅极的节点和节点的升压电路提供时钟信号。 当前一级的输出信号被激活时，第二晶体管导通。 此后，当时钟信号被激活并且节点被充电时，第二晶体管关断。 当第二晶体管截止时，升压电路增加了节点处的电位。 因此，第一晶体管可以在非饱和区域中工作并激活输出信号。

公开(公告)号：US08040999B2

公开(公告)日：2011-10-18

申请号：US12606551

申请日：2009-10-27

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G11C19/00

CPC分类号： G11C19/28 ,  G11C19/184

摘要： A shift register circuit is provided that can suppress a decrease in a drive capability when a frequency of a clock signal increases. A unit shift register includes a first transistor for supplying a clock signal to an output terminal, a pull-up driving circuit for driving the first transistor, a second transistor for discharging the output terminal, and a pull-down driving circuit for driving the second transistor. In the pull-up driving circuit, the gate of a third transistor charging the gate of the first transistor is charged in accordance with activation of an output signal of preceding stage, and the potential at the gate of the third transistor is increased with a capacitive element. As a result, the third transistor operates in the non-saturated region.

摘要翻译： 提供一种移位寄存器电路，其可以抑制当时钟信号的频率增加时的驱动能力的降低。 单元移位寄存器包括用于向输出端子提供时钟信号的第一晶体管，用于驱动第一晶体管的上拉驱动电路，用于对输出端子进行放电的第二晶体管，以及用于驱动第二晶体管的下拉驱动电路 晶体管。 在上拉驱动电路中，对第一晶体管的栅极充电的第三晶体管的栅极根据前级的输出信号的激活而被充电，并且第三晶体管的栅极处的电位以电容 元件。 结果，第三晶体管在非饱和区域中工作。

公开(公告)号：US07499518B2

公开(公告)日：2009-03-03

申请号：US11532750

申请日：2006-09-18

申请人： Youichi Tobita ,  Hiroyuki Murai

发明人： Youichi Tobita ,  Hiroyuki Murai

IPC分类号： G11C19/00

CPC分类号： G11C19/184 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/027 ,  G11C19/28

摘要： A shift register includes, in the output stage, a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a first power terminal. Third and fourth transistors constitute an inverter which inverses the level of the gate of the second transistor and outputs it to the gate of the first transistor. An isolation circuit formed by fifth and sixth transistors is provided between the gate of the first transistor and the gate of the fourth transistor. The fifth transistor is diode-connected. When the gate of the first transistor becomes higher than the gate of the fourth transistor, the first and fourth transistors are electrically isolated from each other.

摘要翻译： 移位寄存器包括在输出级中连接在输出端和第一时钟端之间的第一晶体管和连接在输出端和第一电源端之间的第二晶体管。 第三和第四晶体管构成反相器，其反转第二晶体管的栅极的电平并将其输出到第一晶体管的栅极。 由第五晶体管和第六晶体管形成的隔离电路设置在第一晶体管的栅极和第四晶体管的栅极之间。 第五个晶体管是二极管连接的。 当第一晶体管的栅极变得高于第四晶体管的栅极时，第一和第四晶体管彼此电隔离。

公开(公告)号：US07492853B2

公开(公告)日：2009-02-17

申请号：US11625117

申请日：2007-01-19

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G11C19/00

CPC分类号： G11C19/28

摘要： A unit shift register includes first and second transistors for supplying low supply voltage to an output terminal. First and second control signals which are complementary to each other are input to first and second control terminals, respectively. A third transistor is connected between the first transistor and first control terminal, and a fourth transistor is connected between the second transistor and second control terminal. The third and fourth transistors each have its drain connected to the gate of each other in a crossed manner.

摘要翻译： 单元移位寄存器包括用于向输出端子提供低电源电压的第一和第二晶体管。 彼此互补的第一和第二控制信号分别输入到第一和第二控制端子。 第三晶体管连接在第一晶体管和第一控制端之间，第四晶体管连接在第二晶体管与第二控制端之间。 第三和第四晶体管各自以交叉的方式将其漏极连接到彼此的栅极。

公开(公告)号：US20080303769A1

公开(公告)日：2008-12-11

申请号：US12133734

申请日：2008-06-05

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3655 ,  G09G2310/0286 ,  G09G2330/021 ,  G11C19/28

摘要： The present invention aims to provide an image display device capable of reducing power consumption, and a drive circuit used in the same. The present invention relates to an image display device including signal lines, scanning lines, lines, transistors, capacitances, and a drive circuit. The drive circuit of the image display device has configuring active elements of a same conductivity type and has the active elements simultaneously formed on a same substrate as said transistor; and includes switching circuits for generating a first switching signal and a second switching signal for switching a voltage level of a drive signal based on a predetermined signal, and outputting the signals, an output level holding circuit for holding the voltage levels of the first switching signal and the second switching signal for a predetermined period based on a repeating signal, and an output circuit for generating the drive signal based on the first switching signal and the second switching signal, and outputting the drive signal to the line.

摘要翻译： 本发明的目的在于提供能够降低功耗的图像显示装置及其驱动电路。 本发明涉及包括信号线，扫描线，线，晶体管，电容和驱动电路的图像显示装置。 图像显示装置的驱动电路具有相同导电类型的配置有源元件，并且同时在与所述晶体管相同的衬底上形成有源元件; 并且包括用于产生第一开关信号的开关电路和用于基于预定信号切换驱动信号的电压电平的第二开关信号，并输出该信号;输出电平保持电路，用于保持第一开关信号的电压电平 和基于重复信号的预定周期的第二切换信号，以及用于基于第一切换信号和第二切换信号产生驱动信号的输出电路，并将驱动信号输出到线路。

公开(公告)号：US07436923B2

公开(公告)日：2008-10-14

申请号：US11937791

申请日：2007-11-09

申请人： Youichi Tobita

发明人： Youichi Tobita

IPC分类号： G11C19/00

CPC分类号： H03K19/096 ,  G09G3/3677 ,  G09G2300/0417 ,  G09G2310/0283 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28

摘要： Threshold voltage shifts of transistors which are constituents of a bidirectional shift register are reduced to prevent a malfunction in the shift register. A bidirectional unit shift register includes first and second pull-down circuits (41, 42) connected to the gate of a first transistor (Q1) that supplies a first clock signal (CLK) to an output terminal (OUT). The first pull-down circuit (41) includes a first inverter that uses the gate of the first transistor (Q1) as the input node and that is activated by the first clock signal (CLK), and a second transistor (Q5A) that discharges the gate of the first transistor (Q1) according to the output of the first inverter. The second pull-down circuit (42) includes a second inverter that uses the gate of the first transistor (Q1) as the input node and that is activated by a second clock signal (/CLK) having a different phase from the first clock signal (CLK), and a third transistor (Q5A) that discharges the gate of the first transistor according to the output of the second inverter.

摘要翻译： 作为双向移位寄存器的组成部分的晶体管的阈值电压偏移被减小以防止移位寄存器中的故障。 双向单元移位寄存器包括连接到向输出端（OUT）提供第一时钟信号（CLK）的第一晶体管（Q1）的栅极的第一和第二下拉电路（41,42）。 第一下拉电路（41）包括使用第一晶体管（Q1）的栅极作为输入节点并由第一时钟信号（CLK）激活的第一反相器，以及第二晶体管（Q 5 A ），其根据第一反相器的输出对第一晶体管（Q1）的栅极进行放电。 第二下拉电路（42）包括使用第一晶体管（Q1）的栅极作为输入节点并由与第一时钟具有不同相位的第二时钟信号（/ CLK）激活的第二反相器 信号（CLK）以及根据第二反相器的输出对第一晶体管的栅极进行放电的第三晶体管（Q 5A）。