公开(公告)号：US20180261961A1

公开(公告)日：2018-09-13

申请号：US15878624

申请日：2018-01-24

Applicant: Hirose Electric Co., Ltd.

Inventor： Clement LUK ,  Jeremy BUAN ,  Tadashi OHSHIDA ,  Ching-Chao HUANG

IPC: H01R13/6474 ,  H01R43/16 ,  H01R13/22

CPC classification number: H01R13/6474 ,  H01R13/04 ,  H01R13/22 ,  H01R43/16

Abstract: Example implementations described herein are directed to a method and apparatus for improving insertion loss of connector stub and thereby increasing a system's signal bandwidth. This technique shapes the connector stub in a specific way to shift its resonant frequency higher while having equal or better electrical performance below the original resonant frequency.

公开(公告)号：US20220200587A1

公开(公告)日：2022-06-23

申请号：US17691804

申请日：2022-03-10

Applicant: Hirose Electric Co., Ltd.

Inventor： Ching-Chao HUANG ,  Jeremy BUAN ,  Jingqian TIAN ,  Tadashi OHSHIDA

IPC: H03K5/1252

Abstract: A method of manufacturing an electrical system for reducing differential-to-differential far end crosstalk (DDFEXT) includes converting a first S parameter representative of a design of a first electrical system into a differential-only S parameter, generating a second differential-only S parameter configured to add even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter of the electrical system such that a total even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter are substantially equivalent, and reconfiguring a second electrical system from the differential-only S parameter and the second differential-only S parameter.

公开(公告)号：US20220038083A1

公开(公告)日：2022-02-03

申请号：US17359149

申请日：2021-06-25

Applicant: Hirose Electric Co., Ltd.

Inventor： Ching-Chao HUANG ,  Jeremy BUAN ,  Jingqian TIAN ,  Tadashi OHSHIDA

IPC: H03K5/1252

Abstract: Example implementations described herein are directed to reducing far end cross talk (FEXT), including differential-to-differential far end crosstalk (DDFEXT) or single ended FEXT through generating and applying a delay shifter/inverter that is cascaded onto a target electrical system and shifts the even-mode and odd-mode propagation delay of a target electrical system to be substantially equal, which in turn reduces FEXT in the overall system.

公开(公告)号：US20210389642A1

公开(公告)日：2021-12-16

申请号：US17331534

申请日：2021-05-26

Applicant: Hirose Electric Co., Ltd.

Inventor： Kihong KIM ,  Jeremy BUAN ,  Tsutomu MATSUO ,  Tadashi OHSHIDA

IPC: G02F1/295 ,  G02F1/335 ,  G02B6/42

Abstract: Example implementations described herein are directed to an interface configured to redirect light between a connector connected to a printed optical board (POB) via an optical waveguide, and a photonic integrated circuit (PIC), the interface involving two-dimensionally distributed waveplates (TDWs) having multiple layers of p-doped and n-doped silicon, the TDWs configured to be driven to change a dielectric constant at a two dimensional location on the TDWs such that the received light is redirected at the two dimensional location.

公开(公告)号：US20210325608A1

公开(公告)日：2021-10-21

申请号：US17216207

申请日：2021-03-29

Applicant: Hirose Electric Co., Ltd.

Inventor： Kihong KIM ,  Jeremy BUAN ,  Tadashi OHSHIDA ,  Tsutomu MATSUO ,  Shuji SUZUKI ,  Nobuhiro TAMAI ,  Hiromichi MURAOKA

IPC: G02B6/122

Abstract: Example implementations described herein are directed to a system involving one or more photonic integrated circuits having multi-mode waveguides and connected to a printed optical board through the use of multi-mode waveguide connectors described herein. The printed optical board can include an embedded multi-mode waveguide bus to facilitate optical signal to and from the photonic integrated circuits. The system can also include a chiplet such as a photonic integrated circuit with a single mode waveguide configured to connect to an optical fiber cable.