公开(公告)号：US20100095037A1

公开(公告)日：2010-04-15

申请号：US11916183

申请日：2006-05-26

申请人： Hiroshi Kyusojin ,  Hideki Matsumoto ,  Masato Kajimoto ,  Chiaki Yamana

发明人： Hiroshi Kyusojin ,  Hideki Matsumoto ,  Masato Kajimoto ,  Chiaki Yamana

IPC分类号： G06F13/24

CPC分类号： G06F13/28

摘要： The present invention relates to an information processing apparatus, an information processing method and a program for simplifying an interrupt process to reduce time needed for the interrupt process. If it is determined in step S52 that a network card pointer and a CPU clear pointer fail to match each other, i.e., that there is a packet area corresponding to a packet used in an executed DMA transfer process and having not undergone a DMA transfer complete process, processing proceeds to step S53. An interrupt generator sets a completion status as an interrupt status and proceeds to step S54. In step S54, the interrupt generator generates an interrupt signal. If it is determined in step S52 that there is not a packet area corresponding to a packet used in an executed DMA transfer process and having not undergone a DMA transfer complete process, processing proceeds to step S55. The interrupt generator clears the completion status. The present invention is applicable to a network card, for example.

摘要翻译： 本发明涉及一种信息处理装置，信息处理方法以及用于简化中断处理以减少中断处理所需时间的程序。 如果在步骤S52中确定网卡指针和CPU清除指针彼此不匹配，即，存在与执行的DMA传输处理中使用并且未经历DMA传输完成的分组相对应的分组区域 处理进入步骤S53。 中断发生器将完成状态设置为中断状态，并进入步骤S54。 在步骤S54中，中断发生器产生中断信号。 如果在步骤S52中确定没有与执行的DMA传输处理中使用的分组对应的分组区域，并且没有进行DMA传输完成处理，则处理进行到步骤S55。 中断产生器清除完成状态。 本发明例如适用于网卡。

公开(公告)号：US20070242682A1

公开(公告)日：2007-10-18

申请号：US11669679

申请日：2007-01-31

申请人： Hiroshi Kyusojin ,  Masato Kajimoto ,  Chiaki Yamana ,  Tsuyoshi Kano ,  Mitsuki Hinosugi ,  Hideki Matsumoto

发明人： Hiroshi Kyusojin ,  Masato Kajimoto ,  Chiaki Yamana ,  Tsuyoshi Kano ,  Mitsuki Hinosugi ,  Hideki Matsumoto

IPC分类号： H04L12/56

CPC分类号： H03M13/09 ,  H04L1/0045 ,  H04L1/0061 ,  H04L2001/0095

摘要： An information processing device is provided. The information processing device includes a frame acquiring unit for acquiring a frame using a signal transmitted via a network, a computing unit for computing a check sequence on the basis of data included in the frame, a checking unit for checking whether the frame is corrupted by checking whether the check sequence coincides with a check sequence added to the frame in advance, a storing unit for storing a table that is a list of check sequences computed in advance on the basis of a plurality of pieces of data representing addresses of frames to be received by the information processing device, and a determining unit for determining whether the frame should be received by determining whether a check sequence computed by the computing unit on the basis of data representing a destination address of the frame coincides with any one of the check sequences included in the table.

摘要翻译： 提供信息处理装置。 信息处理装置包括：帧获取单元，用于使用经由网络发送的信号获取帧;计算单元，用于基于包括在帧中的数据计算检查序列;检查单元，用于检查帧是否被 检查所述检查序列是否与预先添加到所述帧的检查序列一致;存储单元，用于存储作为预先计算的检查序列的列表的表，所述表是基于要表示的帧的地址的多个数据块 由信息处理装置接收的确定单元，以及确定单元，用于通过确定由计算单元基于表示帧的目的地地址的数据计算的检查序列是否与检查序列中的任一个一致，来确定是否应该接收该帧 包括在表中。

公开(公告)号：US20060242334A1

公开(公告)日：2006-10-26

申请号：US11392584

申请日：2006-03-30

申请人： Hiroshi Kyusojin ,  Hideki Matsumoto ,  Masato Kajimoto ,  Chiaki Yamana

发明人： Hiroshi Kyusojin ,  Hideki Matsumoto ,  Masato Kajimoto ,  Chiaki Yamana

IPC分类号： G06F3/00 ,  G06F5/00

CPC分类号： H04L49/901 ,  H04L49/90

摘要： An information processor includes: generating section generating a descriptor, the descriptor including positional information, which indicates a packet-by-packet recording position of the data in the memory, and delay time relating to packet-by-packet processing; an extracting section acquiring the descriptor generated by the generating section and extracting the positional information and the delay time from the acquired descriptor; an DMA section reading packet-by-packet data from the memory on the basis of the extracted positional information; and a delaying section delaying processing of at least one of the extracting section and the DMA section by the delay time that has been extracted by the extracting section.

摘要翻译： 信息处理器包括：产生描述符的生成部分，包括位置信息的描述符，其指示存储器中数据的逐个分组记录位置以及与分组处理有关的延迟时间; 获取由所述生成部生成的所述描述符并从所获取的描述符提取所述位置信息和所述延迟时间的提取部; DMA部分基于所提取的位置信息从存储器读取分组数据; 以及延迟部分，延迟所述提取部分和所述DMA部分中的至少一个处理已经由所述提取部分提取的延迟时间。

公开(公告)号：US08412871B2

公开(公告)日：2013-04-02

申请号：US11913164

申请日：2006-05-23

申请人： Hiroshi Kyusojin ,  Hideki Matsumoto ,  Masato Kajimoto ,  Chiaki Yamana ,  Tsuyoshi Kano ,  Mitsuki Hinosugi

发明人： Hiroshi Kyusojin ,  Hideki Matsumoto ,  Masato Kajimoto ,  Chiaki Yamana ,  Tsuyoshi Kano ,  Mitsuki Hinosugi

IPC分类号： G06F15/163 ,  G06F13/24

CPC分类号： G06F13/24

摘要： The present invention relates to an information processing apparatus, an information processing method, and a program capable of simplifying an interrupt processing and reducing a time necessary to the interrupt processing. An interrupt generation unit 140 generates an interrupt signal. An interrupt status holding unit 142 stores an interrupt status showing a cause of generation of the interrupt signal. An interrupt status supply unit 141 supplies an interrupt status stored by an interrupt status holding unit to a RAM and causes the RAM to store it. A CPU executes a predetermined processing in response to the interrupt status stored to the RAM. The present invention can be applied to, for example, a network card.

摘要翻译： 本发明涉及一种信息处理装置，信息处理方法以及能够简化中断处理并减少中断处理所需的时间的程序。 中断产生单元140产生中断信号。 中断状态保持单元142存储表示产生中断信号的原因的中断状态。 中断状态提供单元141将由中断状态保持单元存储的中断状态提供给RAM，并使RAM存储它。 CPU响应于存储到RAM的中断状态来执行预定的处理。 本发明可以应用于例如网卡。

公开(公告)号：US08028114B2

公开(公告)日：2011-09-27

申请号：US11916183

申请日：2006-05-26

申请人： Hiroshi Kyusojin ,  Hideki Matsumoto ,  Masato Kajimoto ,  Chiaki Yamana

发明人： Hiroshi Kyusojin ,  Hideki Matsumoto ,  Masato Kajimoto ,  Chiaki Yamana

IPC分类号： G06F13/24

CPC分类号： G06F13/28

摘要： The present invention relates to an information processing apparatus, an information processing method and a program for simplifying an interrupt process to reduce time needed for the interrupt process. If it is determined in step S52 that a network card pointer and a CPU clear pointer fail to match each other, i.e., that there is a packet area corresponding to a packet used in an executed DMA transfer process and having not undergone a DMA transfer complete process, processing proceeds to step S53. An interrupt generator sets a completion status as an interrupt status and proceeds to step S54. In step S54, the interrupt generator generates an interrupt signal. If it is determined in step S52 that there is not a packet area corresponding to a packet used in an executed DMA transfer process and having not undergone a DMA transfer complete process, processing proceeds to step S55. The interrupt generator clears the completion status. The present invention is applicable to a network card, for example.

摘要翻译： 本发明涉及一种信息处理装置，信息处理方法以及用于简化中断处理以减少中断处理所需时间的程序。 如果在步骤S52中确定网卡指针和CPU清除指针彼此不匹配，即，存在与执行的DMA传输处理中使用并且未经历DMA传输完成的分组相对应的分组区域 处理进入步骤S53。 中断发生器将完成状态设置为中断状态，并进入步骤S54。 在步骤S54中，中断发生器产生中断信号。 如果在步骤S52中确定没有与执行的DMA传输处理中使用的分组对应的分组区域，并且没有进行DMA传输完成处理，则处理进行到步骤S55。 中断产生器清除完成状态。 本发明例如适用于网卡。

公开(公告)号：US07584307B2

公开(公告)日：2009-09-01

申请号：US11392584

申请日：2006-03-30

申请人： Hiroshi Kyusojin ,  Hideki Matsumoto ,  Masato Kajimoto ,  Chiaki Yamana

发明人： Hiroshi Kyusojin ,  Hideki Matsumoto ,  Masato Kajimoto ,  Chiaki Yamana

IPC分类号： G06F3/00

CPC分类号： H04L49/901 ,  H04L49/90

摘要： An information processor includes: generating section generating a descriptor, the descriptor including positional information, which indicates a packet-by-packet recording position of the data in the memory, and delay time relating to packet-by-packet processing; an extracting section acquiring the descriptor generated by the generating section and extracting the positional information and the delay time from the acquired descriptor; an DMA section reading packet-by-packet data from the memory on the basis of the extracted positional information; and a delaying section delaying processing of at least one of the extracting section and the DMA section by the delay time that has been extracted by the extracting section.

摘要翻译： 信息处理器包括：产生描述符的生成部分，包括位置信息的描述符，其指示存储器中数据的逐个分组记录位置以及与分组处理有关的延迟时间; 获取由所述生成部生成的所述描述符并从所获取的描述符提取所述位置信息和所述延迟时间的提取部; DMA部分基于所提取的位置信息从存储器读取分组数据; 以及延迟部分，延迟所述提取部分和所述DMA部分中的至少一个处理已经由所述提取部分提取的延迟时间。

公开(公告)号：US07961614B2

公开(公告)日：2011-06-14

申请号：US11669679

申请日：2007-01-31

申请人： Hiroshi Kyusojin ,  Masato Kajimoto ,  Chiaki Yamana ,  Tsuyoshi Kano ,  Mitsuki Hinosugi ,  Hideki Matsumoto

发明人： Hiroshi Kyusojin ,  Masato Kajimoto ,  Chiaki Yamana ,  Tsuyoshi Kano ,  Mitsuki Hinosugi ,  Hideki Matsumoto

IPC分类号： H04L9/00

CPC分类号： H03M13/09 ,  H04L1/0045 ,  H04L1/0061 ,  H04L2001/0095

摘要： An information processing device is provided. The information processing device includes a frame acquiring unit for acquiring a frame using a signal transmitted via a network, a computing unit for computing a check sequence on the basis of data included in the frame, a checking unit for checking whether the frame is corrupted by checking whether the check sequence coincides with a check sequence added to the frame in advance, a storing unit for storing a table that is a list of check sequences computed in advance on the basis of a plurality of pieces of data representing addresses of frames to be received by the information processing device, and a determining unit for determining whether the frame should be received by determining whether a check sequence computed by the computing unit on the basis of data representing a destination address of the frame coincides with any one of the check sequences included in the table.

摘要翻译： 提供信息处理装置。 信息处理装置包括：帧获取单元，用于使用经由网络发送的信号获取帧;计算单元，用于基于包括在帧中的数据计算检查序列;检查单元，用于检查帧是否被 检查所述检查序列是否与预先添加到所述帧的检查序列一致;存储单元，用于存储作为预先计算的检查序列的列表的表，所述表是基于要表示的帧的地址的多个数据块 由信息处理装置接收的确定单元，以及确定单元，用于通过确定由计算单元基于表示帧的目的地地址的数据计算的检查序列是否与检查序列中的任一个一致，来确定是否应该接收该帧 包括在表中。

公开(公告)号：US20090172302A1

公开(公告)日：2009-07-02

申请号：US11913164

申请日：2006-05-23

申请人： Hiroshi Kyusojin ,  Hideki Matsumoto ,  Masato Kajimoto ,  Chiaki Yamana ,  Tsuyoshi Kano ,  Mitsuki Hinosugi

发明人： Hiroshi Kyusojin ,  Hideki Matsumoto ,  Masato Kajimoto ,  Chiaki Yamana ,  Tsuyoshi Kano ,  Mitsuki Hinosugi

IPC分类号： G06F12/00 ,  G06F13/24

CPC分类号： G06F13/24

摘要： The present invention relates to an information processing apparatus, an information processing method, and a program capable of simplifying an interrupt processing and reducing a time necessary to the interrupt processing. An interrupt generation unit 140 generates an interrupt signal. An interrupt status holding unit 142 stores an interrupt status showing a cause of generation of the interrupt signal. An interrupt status supply unit 141 supplies an interrupt status stored by an interrupt status holding unit to a RAM and causes the RAM to store it. A CPU executes a predetermined processing in response to the interrupt status stored to the RAM. The present invention can be applied to, for example, a network card.

摘要翻译： 本发明涉及一种信息处理装置，信息处理方法以及能够简化中断处理并减少中断处理所需的时间的程序。 中断产生单元140产生中断信号。 中断状态保持单元142存储表示产生中断信号的原因的中断状态。 中断状态提供单元141将由中断状态保持单元存储的中断状态提供给RAM，并使RAM存储它。 CPU响应于存储到RAM的中断状态来执行预定的处理。 本发明可以应用于例如网卡。

公开(公告)号：US20070204084A1

公开(公告)日：2007-08-30

申请号：US11669766

申请日：2007-01-31

申请人： Hiroshi Kyusojin ,  Masato Kajimoto ,  Chiaki Yamana ,  Kazuyoshi Horie ,  Taku Tanaka ,  Kazutaka Tachibana

发明人： Hiroshi Kyusojin ,  Masato Kajimoto ,  Chiaki Yamana ,  Kazuyoshi Horie ,  Taku Tanaka ,  Kazutaka Tachibana

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： An information processing apparatus is provided. Plural processors respectively execute separate operating systems to process data that has been received from a network. The apparatus includes receiving device that receives the data in predetermined units from the network and analyzing device that analyzes identification data added to the data received by the receiving device. The apparatus also includes maintaining device which maintains a table that relates the identification data to information on identification of an interrupt register in each of the processors that execute the operating systems. The apparatus further includes interrupting device that allows interrupt processing to any of the processors to occur by writing the data received with the receiving device into the interrupt register that is related to the identification data, which is identified on the based of the table maintained by the maintaining device, analyzed by the analyzing device.

摘要翻译： 提供了一种信息处理装置。 多个处理器分别执行单独的操作系统来处理从网络接收到的数据。 该装置包括从网络以预定单位接收数据的接收装置和分析由接收装置接收到的数据添加的识别数据的分析装置。 该装置还包括维护装置，其将与标识数据相关联的表保持在执行操作系统的每个处理器中的关于中断寄存器的标识的信息。 该装置还包括中断装置，其允许通过将与接收装置接收的数据写入与识别数据相关的中断寄存器来允许对任何处理器的中断处理，所述中断寄存器基于由 维护装置，由分析装置分析。

公开(公告)号：US07783810B2

公开(公告)日：2010-08-24

申请号：US11669766

申请日：2007-01-31

申请人： Hiroshi Kyusojin ,  Masato Kajimoto ,  Chiaki Yamana ,  Kazuyoshi Horie ,  Taku Tanaka ,  Kazutaka Tachibana

发明人： Hiroshi Kyusojin ,  Masato Kajimoto ,  Chiaki Yamana ,  Kazuyoshi Horie ,  Taku Tanaka ,  Kazutaka Tachibana

IPC分类号： G06F13/24 ,  G06F15/16

CPC分类号： G06F13/24

摘要： An information processing apparatus is provided. Plural processors respectively execute separate operating systems to process data that has been received from a network. The apparatus includes receiving device that receives the data in predetermined units from the network and analyzing device that analyzes identification data added to the data received by the receiving device. The apparatus also includes maintaining device which maintains a table that relates the identification data to information on identification of an interrupt register in each of the processors that execute the operating systems. The apparatus further includes interrupting device that allows interrupt processing to any of the processors to occur by writing the data received with the receiving device into the interrupt register that is related to the identification data, which is identified on the based of the table maintained by the maintaining device, analyzed by the analyzing device.

摘要翻译： 提供了一种信息处理装置。 多个处理器分别执行单独的操作系统来处理从网络接收到的数据。 该装置包括从网络以预定单位接收数据的接收装置和分析由接收装置接收到的数据添加的识别数据的分析装置。 该装置还包括维护装置，其将与标识数据相关联的表保持在执行操作系统的每个处理器中的关于中断寄存器的标识的信息。 该装置还包括中断装置，其允许通过将与接收装置接收的数据写入与识别数据相关的中断寄存器来允许对任何处理器的中断处理，所述中断寄存器基于由 维护装置，由分析装置分析。