公开(公告)号：US20080294913A1

公开(公告)日：2008-11-27

申请号：US12014250

申请日：2008-01-15

申请人： Hiroshi NAKAGOE ,  Toru Owada ,  Yasushi Nagai

发明人： Hiroshi NAKAGOE ,  Toru Owada ,  Yasushi Nagai

IPC分类号： H04L9/06

CPC分类号： H04L9/0637 ,  H04L2209/125

摘要： Provided is a disk array controller capable of speeding up the processing by simultaneously execution the encryption/decryption of a non parallel block cipher modes of operation. In a disk array controller for controlling a disk array according to a disk access request from a host system, a plurality of non parallel mode encryption/decryption target data are divided into a plurality of messages unrelated to the encryption/decryption processing, partitioning non parallel mode encryption/decryption target data belonging to the respective messages into a plurality of block data, storing each block data belonging to the respective messages by allocating it each line of Rnd[0] to Rnd[R−1] per message, and encrypting/decrypting block data corresponding to block data corresponding to a cell of the same column of each line among the block data stored in a data buffer simultaneously with the pipeline processing performed by a pipeline encryption/decryption circuit.

摘要翻译： 提供了一种能够通过同时执行非并行块加密操作模式的加密/解密来加速处理的盘阵列控制器。 在用于根据来自主机系统的磁盘访问请求来控制磁盘阵列的磁盘阵列控制器中，多个非并行模式加密/解密目标数据被分成与加密/解密处理无关的多个消息，分割非并行 将属于各个消息的模式加密/解密目标数据转换为多个块数据，通过将每个消息的Rnd [0]到Rnd [R-1]的每一行分配来存储属于各个消息的每个块数据，以及加密/ 在与由流水线加密/解密电路执行的流水线处理同时处理与数据缓冲器中存储的块数据中的与每行相同列的单元相对应的块数据的块数据解密。

公开(公告)号：US20120331186A1

公开(公告)日：2012-12-27

申请号：US13603456

申请日：2012-09-05

申请人： Yasushi NAGAI ,  Hiroshi NAKAGOE ,  Shigeki TAIRA

发明人： Yasushi NAGAI ,  Hiroshi NAKAGOE ,  Shigeki TAIRA

IPC分类号： G06F13/28

CPC分类号： G06F13/28 ,  Y02D10/14

摘要： The DMA controller includes a peripheral device read unit to read states of peripheral devices, a state comparator, a transfer unit, a register, and a peripheral device write unit to write data in the peripheral devices according to the contents in the register when the DMA transfer is executed, an interrupt select unit selects one of plural interrupt signals to determine whether the peripheral device read unit, the state comparator and the transfer unit are at a timing to execute operations. Based on these operations the state comparator determines whether to start the DMA transfer, and the transfer unit executes data transfer between the peripheral devices.

公开(公告)号：US20090119355A1

公开(公告)日：2009-05-07

申请号：US12025891

申请日：2008-02-05

申请人： Hiroshi NAKAGOE ,  Yasushi Nagai

发明人： Hiroshi NAKAGOE ,  Yasushi Nagai

IPC分类号： G06F7/00

CPC分类号： G11B20/00086 ,  G06F7/00 ,  G11B20/0021 ,  G11B20/1833 ,  G11B2020/1843 ,  G11B2220/2516 ,  H04L9/0631 ,  H04L2209/122 ,  H04L2209/125 ,  H04L2209/34

摘要： This arithmetic logical unit outputs data to be used in checking the final result of an AES unit that encrypts a plain text block into an encrypted text block based on AES operation, and includes an arithmetic unit for computing parity data created based on XOR operation from an encryption key to be used as a key during AES encryption, parity data created based on XOR operation from a plain text block, and an AES operation halfway result output from the AES unit, and outputting a value that is equivalent to parity data created based on XOR operation from the final result of the AES unit.

摘要翻译： 该算术逻辑单元输出用于将基于AES操作将加密文本块加密的AES单元的最终结果的数据输出到加密文本块中，并且包括用于计算从基于AES操作的异或运算创建的奇偶校验数据的运算单元 在AES加密期间用作密钥的加密密钥，基于来自纯文本块的异或操作创建的奇偶校验数据，以及AES单元输出的AES操作中途结果，并输出等价于基于 来自AES单元的最终结果的异或运算。