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公开(公告)号：US07443239B2
公开(公告)日：2008-10-28
申请号：US11648530
申请日：2007-01-03
IPC分类号： H03F3/45
CPC分类号： H03F3/45233 , H03F2203/45726
摘要： A differential amplifying circuit that includes a differential pair and a cascode current mirror circuit that forms the load circuit of this differential pair. The cascode current mirror circuit includes a control-terminal-coupled first transistor pair, and second and third transistor pairs that receive first and second bias signals at coupled control terminals, respectively. The second transistor pair is straight-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit, and the third transistor pair is cross-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit. The second and third transistor pairs are controlled so as to each be placed in active and inactive states by changing over voltage values of the first and second bias signals, with control being exercised in such a manner that when one of these transistor pairs is in an active state, the other is in an inactive state.
摘要翻译： 一种差分放大电路，其包括形成该差分对的负载电路的差分对和共源共栅电流镜电路。 共源共栅电流镜电路包括控制端耦合的第一晶体管对以及分别在耦合控制端接收第一和第二偏置信号的第二和第三晶体管对。 第二晶体管对直接连接在第一晶体管对与共源共栅电流镜电路的输入端和输出端之间，第三晶体管对交叉连接在第一晶体管对与输入端之间，输出端 的共源共栅电流镜电路。 通过改变第一和第二偏置信号的电压值来控制第二和第三晶体管对，以便各自通过改变第一和第二偏置信号的电压值而被置于有功和无效状态，其中控制是以这样的方式进行的：当这些晶体管对中的一个处于 活动状态，另一个处于非活动状态。
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公开(公告)号：US20070159250A1
公开(公告)日：2007-07-12
申请号：US11648530
申请日：2007-01-03
IPC分类号： H03F3/45
CPC分类号： H03F3/45233 , H03F2203/45726
摘要： A differential amplifying circuit that includes a differential pair and a cascode current mirror circuit that forms the load circuit of this differential pair. The cascode current mirror circuit includes a control-terminal-coupled first transistor pair, and second and third transistor pairs that receive first and second bias signals at coupled control terminals, respectively. The second transistor pair is straight-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit, and the third transistor pair is cross-connected between the first transistor pair and the input end and the output end of the cascode current mirror circuit. The second and third transistor pairs are controlled so as to each be placed in active and inactive states by changing over voltage values of the first and second bias signals, with control being exercised in such a manner that when one of these transistor pairs is in an active state, the other is in an inactive state.
摘要翻译： 一种差分放大电路，其包括形成该差分对的负载电路的差分对和共源共栅电流镜电路。 共源共栅电流镜电路包括控制端耦合的第一晶体管对以及在耦合的控制端分别接收第一和第二偏置信号的第二和第三晶体管对。 第二晶体管对直接连接在第一晶体管对与共源共栅电流镜电路的输入端和输出端之间，第三晶体管对交叉连接在第一晶体管对与输入端之间，输出端 的共源共栅电流镜电路。 通过改变第一和第二偏置信号的电压值来控制第二和第三晶体管对，以便各自通过改变第一和第二偏置信号的电压值而被置于有功和无效状态，其中控制是以这样的方式进行的：当这些晶体管对中的一个处于 活动状态，另一个处于非活动状态。
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公开(公告)号：US20080143658A1
公开(公告)日：2008-06-19
申请号：US11979714
申请日：2007-11-07
申请人： Junichiro Ishii , Hiroshi Tsuchi
发明人： Junichiro Ishii , Hiroshi Tsuchi
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2310/027 , Y10T307/74 , Y10T307/747
摘要： Disclosed is an output circuit including a connection switch and an operation unit. The connection switch receives first and second voltages from first and second terminals, respectively, selects and outputs the first voltage or the second voltage for first to third intermediate terminals, including selection of the same voltage and switches assignment of the first and second voltages to the first to third intermediate terminals responsive to a connection switching signal. The operation unit receives the voltages assigned to the first to third intermediate terminals and outputs to an output terminal a voltage obtained by performing a predetermined operation on the voltages.
摘要翻译： 公开了一种包括连接开关和操作单元的输出电路。 连接开关分别接收来自第一和第二端子的第一和第二电压，选择并输出第一至第三中间端子的第一电压或第二电压，包括选择相同的电压，并将第一和第二电压的分配切换到 响应于连接切换信号的第一到第三中间终端。 操作单元接收分配给第一至第三中间端子的电压，并向输出端子输出通过对电压执行预定操作而获得的电压。
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公开(公告)号：US08384576B2
公开(公告)日：2013-02-26
申请号：US13447546
申请日：2012-04-16
申请人： Junichiro Ishii , Hiroshi Tsuchi
发明人： Junichiro Ishii , Hiroshi Tsuchi
IPC分类号： H03M1/66
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2310/027 , Y10T307/74 , Y10T307/747
摘要： An output circuit includes a connection switch and an operation unit. The connection switch receives first and second voltages from first and second terminals, respectively, selects and outputs the first voltage or the second voltage for first to third intermediate terminals, including selection of the same voltage and switches assignment of the first and second voltages to the first to third intermediate terminals responsive to a connection switching signal. The operation unit receives the voltages assigned to the first to third intermediate terminals and outputs to an output terminal a voltage obtained by performing a predetermined operation on the voltages.
摘要翻译： 输出电路包括连接开关和操作单元。 连接开关分别接收来自第一和第二端子的第一和第二电压，选择并输出第一至第三中间端子的第一电压或第二电压，包括选择相同的电压，并将第一和第二电压的分配切换到 响应于连接切换信号的第一到第三中间终端。 操作单元接收分配给第一至第三中间端子的电压，并向输出端子输出通过对电压执行预定操作而获得的电压。
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公开(公告)号：US20120293483A1
公开(公告)日：2012-11-22
申请号：US13485253
申请日：2012-05-31
申请人： Junichiro Ishii , Hiroshi Tsuchi
发明人： Junichiro Ishii , Hiroshi Tsuchi
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2310/027 , Y10T307/74 , Y10T307/747
摘要： An output circuit includes a connection switch and an operation unit. The connection switch includes first to third terminals for receiving first to third voltages, respectively, selects and outputs the first voltage or the second voltage or the third voltage to each of the first to seventh intermediate terminals, including selection of the same voltage for a plurality of the intermediate terminals. The connection switch switches assignment of the first to third voltages to the first to seventh intermediate terminals responsive to a connection switching signal. The operation unit receives the voltages assigned to the first to seventh intermediate terminals and outputs to an output terminal a voltage obtained by performing a predetermined operation on the voltages supplied to the first to seventh intermediate terminals.
摘要翻译： 输出电路包括连接开关和操作单元。 连接开关包括分别接收第一至第三电压的第一至第三端子，分别选择并输出第一至第七中间端子中的每一个的第一电压或第二电压或第三电压，包括选择多个相同的电压 的中间端子。 响应于连接切换信号，连接开关将第一至第三电压的分配切换到第一至第七中间端子。 操作单元接收分配给第一至第七中间端子的电压，并且向输出端子输出通过对提供给第一至第七中间端子的电压执行预定操作而获得的电压。
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公开(公告)号：US08217883B2
公开(公告)日：2012-07-10
申请号：US11979714
申请日：2007-11-07
申请人： Junichiro Ishii , Hiroshi Tsuchi
发明人： Junichiro Ishii , Hiroshi Tsuchi
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2310/027 , Y10T307/74 , Y10T307/747
摘要： Disclosed is an output circuit including a connection switch and an operation unit. The connection switch receives first and second voltages from first and second terminals, respectively, selects and outputs the first voltage or the second voltage for first to third intermediate terminals, including selection of the same voltage and switches assignment of the first and second voltages to the first to third intermediate terminals responsive to a connection switching signal. The operation unit receives the voltages assigned to the first to third intermediate terminals and outputs to an output terminal a voltage obtained by performing a predetermined operation on the voltages.
摘要翻译： 公开了一种包括连接开关和操作单元的输出电路。 连接开关分别接收来自第一和第二端子的第一和第二电压，选择并输出第一至第三中间端子的第一电压或第二电压，包括选择相同的电压，并将第一和第二电压的分配切换到 响应于连接切换信号的第一到第三中间终端。 操作单元接收分配给第一至第三中间端子的电压，并向输出端子输出通过对电压执行预定操作而获得的电压。
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7.发明申请公开(公告)号：US20070126689A1
公开(公告)日：2007-06-07
申请号：US11633518
申请日：2006-12-05
申请人： Junichiro Ishii , Hiroshi Tsuchi
发明人： Junichiro Ishii , Hiroshi Tsuchi
IPC分类号： G09G3/36
CPC分类号： H03M1/0646 , G09G3/2011 , G09G3/3688 , G09G2310/027 , G09G2320/0276 , H03M1/76
摘要： Disclosed is a digital-to-analog converter including a decoder which receives m (where m>=4 holds) reference voltages having voltage values that differ from one another, and selects and outputs n (where n>=3 holds) identical or different voltages from among the m reference voltages based upon a digital signal; and an amplifying circuit that outputs a voltage, which is obtained by taking the weighted mean of the selected n voltages at a ratio of 2n−1:2n−2: . . . :20, from an output terminal.
摘要翻译： 公开了一种数模转换器，其包括接收m（其中m≥4）的解码器，其具有彼此不同的电压值的参考电压，并且选择并输出n（其中n> = 3成立）相同或不同 基于数字信号的m个参考电压中的电压; 以及放大电路，其输出通过以2比特的比例获取所选择的n个电压的加权平均值而获得的电压：2
2： 。 。 。 ：2 <0> 0 。 -
8.发明授权公开(公告)号：US07847718B2
公开(公告)日：2010-12-07
申请号：US11633518
申请日：2006-12-05
申请人： Junichiro Ishii , Hiroshi Tsuchi
发明人： Junichiro Ishii , Hiroshi Tsuchi
IPC分类号： H03M1/66
CPC分类号： H03M1/0646 , G09G3/2011 , G09G3/3688 , G09G2310/027 , G09G2320/0276 , H03M1/76
摘要： A digital-to-analog converter including includes a decoder which receives m (where m>=4 holds) reference voltages having voltage values that differ from one another, and selects and outputs n (where n>=3 holds) identical or different voltages from among the m reference voltages based upon a digital signal; and an amplifying circuit that outputs a voltage, which is obtained by taking the weighted mean of the selected n voltages at a ratio of 2n−1:2n−2: . . . :20, from an output terminal.
摘要翻译： 一种数模转换器包括一个接收m（其中m≥4）的解码器，其具有彼此不同的电压值的参考电压，并且选择并输出n（其中n≥3）保持相同或不同的电压 基于数字信号的m个参考电压; 以及放大电路，输出通过以2n-1：2n-2：的比例取所选择的n个电压的加权平均值而得到的电压。 。 。 ：20，从输出端子。
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9.发明授权公开(公告)号：US09224356B2
公开(公告)日：2015-12-29
申请号：US14002948
申请日：2012-03-01
申请人： Hiroshi Tsuchi
发明人： Hiroshi Tsuchi
CPC分类号： G09G5/003 , G09G3/3291 , G09G3/3688 , G09G3/3696 , G09G5/00 , G09G2310/027 , G09G2310/0291 , H03M1/661 , H03M1/76
摘要： DAC includes a decoder that receives N number of reference voltages and an n-bit digital signal (n 4) to select first to third voltages, and an operational amplifier to output (first voltage+second voltage+2 third voltage)/4 voltage. The operational amplifier is able to output, for respective 2^n combinations of the n-bit digital signal, voltage levels from an Ath level, as a base level, to an (A−1+2^n)th level. The N number of reference voltages include Ath level, (A+4)th level, (A−4+2^n) and (A+2^n), and an at most {−4+2^(n−2)} reference voltages obtained by decimating a pre-set at least one reference voltage from {−3+2^(n−2)} reference voltages that are other than the four number of reference voltages from the {1+2^(n−2)} reference voltages corresponding to the voltage levels spaced each other at an interval of 4 levels from the Ath level. N is not less than 4 and not more than 2^(n−2).
摘要翻译： DAC包括接收N个参考电压的解码器和用于选择第一至第三电压的n位数字信号（n4），以及输出（第一电压+第二电压+2第三电压）/ 4电压的运算放大器。 对于n位数字信号的相应2 ^ n组合，运算放大器能够从作为基准电平的Ath电平到（A-1 + 2 ^ n）级的电压电平输出。 N个参考电压包括Ath电平，（A + 4）电平，（A-4 + 2 ^ n）和（A + 2 ^ n），以及至多{-4 + 2 ^（n-2） ）}参考电压，其通过从{1 + 2 ^（n-2）}个参考电压除去来自{1 + 2 ^（n-2）}的四个参考电压以外的预设的至少一个参考电压而获得 -2）}相对应的电压电平的参考电压以与Ath级别成4级的间隔彼此隔开。 N不小于4且不大于2 ^（n-2）。
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10.发明授权公开(公告)号：US08786479B2
公开(公告)日：2014-07-22
申请号：US13064354
申请日：2011-03-21
申请人： Hiroshi Tsuchi
发明人： Hiroshi Tsuchi
IPC分类号： H03M1/68
CPC分类号： G09G3/3688 , G09G3/3696 , G09G2310/027 , G09G2330/028
摘要： Reference voltages of a reference voltage ensemble are classed into first to (z×S+1)th reference voltage groups, where S is a power of 2 inclusive of 1 and z is a power of 2 plus 1. A decoder includes first to (z×S+1)th sub-decoders provided in association with the first to (z×S+1)th reference voltage groups, and a (z×S+1) input and 2 output type sub-decoder. The first to (z×S+1)th sub-decoders select, from the reference voltage of the first to the (z×S+1)th reference voltage groups, those reference voltages allocated to columns in a two-dimensional array of the reference voltages associated with the values of a first bit group of an input digital signal. The (z×S+1) input and 2 output sub-decoder receives outputs of the first to (z×S+1)th sub-decoders to select the first and second voltages from the reference voltages selected by the first to (z×S+1)th sub-decoders in response to the value of a second bit group of the input digital signal. An interpolation circuit receives the first and second voltages, selected by the decoder, to output a voltage level obtained on interpolation with an interpolation ratio of 1:1 (FIG. 1).
摘要翻译： 参考电压集合的参考电压被分类为第一至第（z×S + 1）个参考电压组，其中S是2的功率，包括1，z是2加1的功率。解码器包括首先（ 和第（z×S + 1）个输入型子解码器相关联地设置的z×S + 1个子解码器。 第一至第（Z×S + 1）子解码器从第一至第（z×S + 1）个参考电压组的参考电压中选择分配给二维阵列中的列的参考电压 与输入数字信号的第一位组的值相关联的参考电压。 （z×S + 1）输入和2输出子解码器接收第一至第（Z×S + 1）个子解码器的输出，以从由第一至第（z） ×S + 1）个子解码器，响应于输入数字信号的第二位组的值。 接收由解码器选择的第一和第二电压的插值电路，以1：1（图1）的插值比率输出以内插获得的电压电平。
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