公开(公告)号：US08035543B2

公开(公告)日：2011-10-11

申请号：US12686654

申请日：2010-01-13

Applicant: Eun Seok Shin ,  Min Kyu Song ,  Jun Ho Moon ,  Hee Won Kang

Inventor： Eun Seok Shin ,  Min Kyu Song ,  Jun Ho Moon ,  Hee Won Kang

IPC: H03M1/36

CPC classification number: H03M1/0646 ,  H03M1/0682 ,  H03M1/365

Abstract: An analog-to-digital conversion circuit includes a plurality of comparators and an averaging circuit. The averaging circuit is configured so that a length of a metal routing connected between output terminals of two comparators arranged on a leftmost side from among the plurality of comparators or a length of a metal routing connected between output terminals of two comparators arranged on a rightmost side from among the plurality of comparators is less than a length of a metal routing connected between output terminals of two comparators to which reference voltages having levels that are closest in magnitude are input.

Abstract translation: 模拟 - 数字转换电路包括多个比较器和平均电路。 平均电路被配置为使得连接在布置在多个比较器中最左侧的两个比较器的输出端之间的金属布线的长度或连接在布置在最右侧的两个比较器的输出端之间的金属布线的长度 多个比较器之间的距离小于在两个比较器的输出端子之间连接的金属布线的长度，在两个比较器的输出端之间输入的参考电压的幅度最接近其幅度。

公开(公告)号：US20100026543A1

公开(公告)日：2010-02-04

申请号：US12487723

申请日：2009-06-19

Applicant: Chih-Hou TSAI ,  Wei-Ping WANG

Inventor： Chih-Hou TSAI ,  Wei-Ping WANG

IPC: H03M1/12

CPC classification number: H03M1/0646 ,  H03M1/361

Abstract: An analog to digital converter having an input stage amplifier array, an input stage voltage divider array, a comparator array and an encoder. The input stage amplifier array calculates and amplifies the difference between an input signal and a plurality of reference signals to generate a plurality of amplified differences. The input stage voltage divider array averages every two adjacent amplified differences to generate a plurality of average signals. The comparator array compares the average signals with a threshold value and outputs the compared results to the encoder for digital data representing the value of the input signal.

Abstract translation: 具有输入级放大器阵列，输入级分压器阵列，比较器阵列和编码器的模数转换器。 输入级放大器阵列计算并放大输入信号和多个参考信号之间的差以产生多个放大的差。 输入级分压器阵列对每两个相邻的放大差值进行平均以产生多个平均信号。 比较器阵列将平均信号与阈值进行比较，并将比较结果输出到编码器，用于表示输入信号值的数字数据。

公开(公告)号：US07236115B1

公开(公告)日：2007-06-26

申请号：US10763561

申请日：2004-01-22

Applicant: Christopher A. Menkus ,  Robert Callaghan Taft

Inventor： Christopher A. Menkus ,  Robert Callaghan Taft

IPC: H03M1/66

CPC classification number: H03M1/0646 ,  H03M1/141 ,  H03M1/366

Abstract: A circuit for reducing the maximum magnitude of the total current on each of a plurality of buses for an amplifier stage in a folding analog to digital converter. Each amplifier stage bus couples multiple transconductance circuits to a load. Also, each of the transconductance circuits is configured to output a separate transconductance current to its respective bus. Separate current source circuits are configured to provide a separate source current locally at the output of each of the transconductance circuits such that substantially less than the full amount of each transconductance current reaches the respective bus.

Abstract translation: 一种用于减小折叠模数转换器中用于放大器级的多条母线中的每一条总电流的最大幅值的电路。 每个放大器级总线将多个跨导电路耦合到负载。 此外，每个跨导电路被配置为将单独的跨导电流输出到其相应的总线。 单独的电流源电路被配置为在每个跨导电路的输出处局部地提供单独的源极电流，使得实质上小于每个跨导电流的全部量到达相应的总线。

公开(公告)号：US06847320B1

公开(公告)日：2005-01-25

申请号：US10816235

申请日：2004-03-30

Applicant: Robert C. Taft ,  Christopher A. Menkus

Inventor： Robert C. Taft ,  Christopher A. Menkus

IPC: H03M1/12

CPC classification number: H03M1/0646 ,  H03M1/361 ,  H03M1/368

Abstract: A method and circuit for improving linearity of a folding or flash analog-digital-converter (ADC) circuit. Averaging resistors connect outputs of each of a bank of first pre-amplifiers. A series adjustment resistor is placed between each node connecting the output of a first bank pre-amplifier and the associated averaging resistor, and the input of each of a second bank pre-amplifier. An adjustment current is injected through the adjustment resistor during a calibration. A permanent value for adjustment current is determined such that an effect of offset errors is substantially minimized.

Abstract translation: 一种用于提高折叠或闪光模拟数字转换器（ADC）电路的线性度的方法和电路。 平均电阻连接一组第一前置放大器的每一个的输出。 在连接第一组前置放大器的输出端和相关联的平均电阻器的每个节点和第二组前置放大器之间的每个节点之间放置一个串联调节电阻器。 在校准期间通过调节电阻注入调整电流。 确定调整电流的永久值，使得偏移误差的影响基本上最小化。

公开(公告)号：US06822600B1

公开(公告)日：2004-11-23

申请号：US10816293

申请日：2004-03-30

Applicant: Robert C. Taft ,  Christopher A. Menkus

Inventor： Robert C. Taft ,  Christopher A. Menkus

IPC: H03M112

CPC classification number: H03M1/089 ,  H03M1/0646 ,  H03M1/141 ,  H03M1/205 ,  H03M1/361

Abstract: A method and circuit for terminating a pre-amplification array for stable linearity of a folding or flash analog-digital-converter (ADC) circuit over a temperature range. Termination resistors with pre-selected temperature coefficients are coupled between outputs of a first and a last amplifier of an amplifier bank in an averaged pre-amplification stage and a termination voltage source. The termination resistors and the termination voltage provide a current that compensates temperature dependent changes in the current flowing from other amplifiers outputs towards the output of the first and last amplifiers stabilizing linearity when temperature changes. Multiple termination resistors with different temperature coefficients may be employed to better approximate the desired temperature coefficient for optimum performance.

Abstract translation: 一种用于在温度范围内终止用于稳定线性的折叠或闪光模拟数字转换器（ADC）电路的预放大阵列的方法和电路。 具有预选温度系数的终端电阻在平均预放大级和终端电压源中耦合在放大器组的第一和最后一个放大器的输出之间。 终端电阻和端接电压提供电流，其补偿从其他放大器输出流向第一和最后放大器的输出的电流随温度变化稳定线性度的温度相关变化。 可以使用具有不同温度系数的多个终端电阻器来更好地近似所需的温度系数以获得最佳性能。

公开(公告)号：US06809667B2

公开(公告)日：2004-10-26

申请号：US10688122

申请日：2003-10-17

Applicant: Klaas Bult ,  Aaron W. Buchwald

Inventor： Klaas Bult ,  Aaron W. Buchwald

IPC: H03M106

CPC classification number: H03M1/0646 ,  H03M1/36

Abstract: A circuit is provided for reducing mismatches between the outputs of successive pairs of cells in an analog to digital converter. A voltage input means is coupled to a first input terminal of each cell to introduce and an input voltage. A reference voltage means is coupled to a second input terminal of each cell to introduce progressive fractions of a reference voltage. A low impedance means is coupled between corresponding first output terminals and coupled between corresponding second output terminals in successive cells, to draw load-bearing currents to the successive cells, affecting the relative voltages and thereby reducing the effects of cell mismatches on these output terminals. Lastly, a high impedance means is coupled to the each of the first output terminals and to each of the second output terminals in successive cells.

Abstract translation: 提供了一种用于减少模数转换器中连续的单元格对的输出之间的不匹配的电路。 电压输入装置耦合到每个单元的第一输入端以引入输入电压。 参考电压装置耦合到每个单元的第二输入端子以引入参考电压的渐进分数。 低阻抗装置耦合在相应的第一输出端子之间，并连接在连续的电池中的相应的第二输出端子之间，以将负载电流牵引到连续的电池，影响相对电压，从而减少电池错配对这些输出端子的影响。 最后，高阻抗装置耦合到连续单元中的每个第一输出端和每个第二输出端。

公开(公告)号：US20020167436A1

公开(公告)日：2002-11-14

申请号：US10146259

申请日：2002-05-15

Inventor： Klaas Bult ,  Aaron W. Buchwald

IPC: H03M001/36

CPC classification number: H03M1/0646 ,  H03M1/36

Abstract: The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive fractions of a reference voltage respectively introduced to the branches in a differential amplifier. To minimize output errors from cell mismatches, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches, and the output terminals in the second branches, in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of current sources connected to the branch output terminals. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets.

Abstract translation: IC芯片上的A-D转换器中的每个单元的输出取决于分别引入差分放大器中的分支的参考电压的输入电压和逐行分数的相对值。 为了使来自单元错配的输出误差最小化，第一和第二组平均阻抗（优选电阻）分别连接在第一分支中的输出端和第二分支中的输出端之间，以连续的单元对。 阻抗具有相对较低的值，特别是与连接到分支输出端子的电流源的阻抗相比较。 芯片上的第一和第二电阻条可以在逐行位置被分接，以分别限定第一和第二组中的阻抗。

公开(公告)号：US6014098A

公开(公告)日：2000-01-11

申请号：US932163

申请日：1997-09-17

Applicant: Klaas Bult ,  Aaron W. Buchwald

Inventor： Klaas Bult ,  Aaron W. Buchwald

IPC: H03M1/06 ,  H03M1/36 ,  H03M1/14

CPC classification number: H03M1/0646 ,  H03M1/36 ,  H03M1/365

Abstract: The output of each cell in an A-D converter on an IC chip is dependent upon the relative values of an input voltage and an individual one of progressive fractions of a reference voltage respectively introduced to the branches in a differential amplifier. To minimize output errors from cell mismatches, first and second sets of averaging impedances, preferably resistors, are respectively connected between the output terminals in the first branches, and the output terminals in the second branches, in successive pairs of cells. The impedances have relatively low values, particularly compared to the impedances of current sources connected to the branch output terminals. First and second resistive strips on the chip may be tapped at progressive positions to respectively define the impedances in the first and second sets. One end of each strip may be connected to the opposite end of the other strip to define a closed impedance loop for minimizing averaging errors at the strip ends. Different fractions of the reference voltage are associated with each individual impedance in the first and second sets. Such reference voltage fractions have a particular repetitive relationship. In this way, the number of output terminals is reduced and cell mismatches are reduced. The different outputs at each individual impedance are determined for the progressive fractions of the reference voltage at such impedance. Successive voltage fractions for each impedance have opposite polarities to provide a folding relationship. Such outputs may be cascaded to further reduce cell mismatches and the number of output terminals.

公开(公告)号：US20190131996A1

公开(公告)日：2019-05-02

申请号：US15996082

申请日：2018-06-01

Applicant: SK hynix Inc.

Inventor： Keunjin Chang

IPC: H03M1/18 ,  H03M1/44

CPC classification number: H03M1/183 ,  H03M1/00 ,  H03M1/0612 ,  H03M1/0646 ,  H03M1/1057 ,  H03M1/447 ,  H03M1/66 ,  H03M1/785 ,  H03M1/80

Abstract: According to an embodiment, a digital-to-analog converter may be provided. The digital-to-analog converter may include a resistive ladder network including a plurality of paths corresponding to bit currents, respectively. The digital-to-analog converter may include a switching circuit configured to include a plurality of weighted elements respectively coupled to the paths. The digital-to-analog converter may include a reference voltage setting circuit coupled to the weighted elements and the paths, and configured to minimize a variation of threshold voltages of the weighted elements.

公开(公告)号：US20110210879A1

公开(公告)日：2011-09-01

申请号：US12766737

申请日：2010-04-23

Applicant: Jeffrey G. Barrow ,  Benjamin O. Barrow

Inventor： Jeffrey G. Barrow ,  Benjamin O. Barrow

IPC: H03M1/00 ,  H03M1/12

CPC classification number: H03M1/0646 ,  H01L27/0207 ,  H01L27/092 ,  H03M1/365

Abstract: Physical layouts of integrated circuits are provided, which may include an analog-to-digital converter including a plurality of comparators. Individual transistors of each comparator of the plurality are arranged in a one-dimensional row in a first direction. Neighboring comparators of the plurality of comparators are positioned relative each other in an abutting configuration in a second direction orthogonal to the first direction. The plurality of comparators may include multiple, inter-coupled, outputs. Such an ADC may be called a Benorion Analog-to-Digital Converter. A method for fabricating an integrated circuit is also provided. The method comprises arranging transistors of a first comparator in a one-dimensional row in a first direction, arranging transistors of at least one additional comparator in the one-dimensional row in the first direction, and arranging transistors of the first comparator and the at least one additional comparator relative to each other in a second direction orthogonal to the first direction.

Abstract translation: 提供了集成电路的物理布局，其可以包括包括多个比较器的模数转换器。 多个的每个比较器的单个晶体管沿第一方向排列成一维的行。 多个比较器的相邻比较器在与第一方向正交的第二方向上以邻接构造相对定位。 多个比较器可以包括多个，互连的输出。 这样的ADC可以称为Benorion模数转换器。 还提供了一种用于制造集成电路的方法。 该方法包括将第一比较器的晶体管布置在第一方向上的一维行中，将第一方向上的至少一个附加比较器的晶体管布置在一维行中，以及将第一比较器的晶体管和至少 在与第一方向正交的第二方向上相对于彼此的一个附加比较器。