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    Data processing processor
    1.
    发明授权
    Data processing processor 失效
    数据处理处理器

    公开(公告)号：US06944696B2

    公开(公告)日：2005-09-13

    申请号：US10673851

    申请日：2003-09-30

    申请人： Hiroshi Yamada ,  Toyokazu Hori ,  Masaru Hase ,  Tetsuya Yamato ,  Norihiko Sugita

    发明人： Hiroshi Yamada ,  Toyokazu Hori ,  Masaru Hase ,  Tetsuya Yamato ,  Norihiko Sugita

    IPC分类号： G06F12/00 ,  G06F13/18 ,  G06F13/362 ,  G06F13/36

    CPC分类号： G06F13/3625

    摘要： A bus arbitration apparatus for an image processing processor is operable such that when a channel having a high necessity of a real-time processing operation issues a bus use request, a bus use permission is not given to another channel having a low necessity of a real-time processing operation. The bus arbitrator of the data includes a timer for counting down use permission time with respect to the channel having the high necessity of the real-time processing operation, and a register for the channel having the low necessity of the real-time processing operation. A value larger than a maximum value of the timer is set to the value of the register. In the bus arbitration, the value of the register is compared with that of the timer, and then the bus use permission is given to a channel having the small value.

    摘要翻译： 用于图像处理处理器的总线仲裁装置是可操作的，使得当具有高实时处理操作的必要性的信道发布总线使用请求时，总线使用许可不被给予具有低真实性的另一信道 时间处理操作。 数据的总线仲裁器包括：相对于具有高实时处理操作的必要性的信道的下降使用许可时间的计时器，以及用于实时处理操作的必要性低的信道的寄存器。 大于定时器最大值的值被设置为寄存器的值。 在总线仲裁中，将寄存器的值与定时器的值进行比较，然后将总线使用许可赋予具有较小值的通道。

    Data processing processor
    2.
    发明授权
    Data processing processor 有权
    数据处理处理器

    公开(公告)号：US06658511B2

    公开(公告)日：2003-12-02

    申请号：US09745928

    申请日：2000-12-26

    申请人： Hiroshi Yamada ,  Toyokazu Hori ,  Masaru Hase ,  Tetsuya Yamato ,  Norihiko Sugita

    发明人： Hiroshi Yamada ,  Toyokazu Hori ,  Masaru Hase ,  Tetsuya Yamato ,  Norihiko Sugita

    IPC分类号： G06F1300

    CPC分类号： G06F13/3625

    摘要： A bus arbitration apparatus for an image processing processor is operable such that when a channel having a high necessity of a real-time processing operation issues a bus use request, a bus use permission is not given to another channel having a low necessity of a real-time processing operation. The bus arbitrator of the data includes a timer for counting down use permission time with respect to the channel having the high necessity of the real-time processing operation, and a register for the channel having the low necessity of the real-time processing operation. A value larger than a maximum value of the timer is set to the value of the register. In the bus arbitration, the value of the register is compared with that of the timer, and then the bus use permission is given to a channel having the small value.

    摘要翻译： 用于图像处理处理器的总线仲裁装置是可操作的，使得当具有高实时处理操作的必要性的信道发布总线使用请求时，总线使用许可不被给予具有低真实性的另一信道 时间处理操作。 数据的总线仲裁器包括：相对于具有高实时处理操作的必要性的信道的下降使用许可时间的计时器，以及用于实时处理操作的必要性低的信道的寄存器。 大于定时器最大值的值被设置为寄存器的值。 在总线仲裁中，将寄存器的值与定时器的值进行比较，然后将总线使用许可赋予具有较小值的通道。

    Discrete cosine transformation operation circuit
    3.
    发明授权
    Discrete cosine transformation operation circuit 失效
    离散余弦变换运算电路

    公开(公告)号：US06185595B2

    公开(公告)日：2001-02-06

    申请号：US08952653

    申请日：1998-03-10

    申请人： Toyokazu Hori ,  Nario Sumi ,  Masaru Hase

    发明人： Toyokazu Hori ,  Nario Sumi ,  Masaru Hase

    IPC分类号： G06F1714

    CPC分类号： G06F17/147

    摘要： One multiplier 13 operated at a normalized frequency 4 is provided to multiply the elements of DCT transformation coefficients and the elements of input data, and the multiplication results are added by a cumulative adder 15 to determine cumulative addition results corresponding to the sum (x0+x7) and the difference (x0−x7) of a pair of elements (x0, x7) of data to be outputted from a one-dimensional DCT operation circuit 1. The paired cumulative addition results are added and subtracted by an adder 17 and a subtracter 18, respectively, to determine the elements (x0, x7). The operations are performed specific times the number of which is one half of the number of elements of a column of the matrix of the input data to determine the elements of a column of the matrix of the output data and are performed specific times the number of which is equal to the number of elements of a row of the matrix or the input data to determine all the elements of the matrix of the output data. As a result, the scale of the DCT operation circuit is reduced, thereby reducing the power consumption.

    摘要翻译： 提供以归一化频率4操作的一个乘法器13，用于将DCT变换系数的元素和输入数据的元素相乘，乘法结果由累积加法器15相加，以确定对应于和（x0 + x7）的累积加法结果 ）和要从一维DCT运算电路1输出的数据的一对元素（x0，x7）的差（x0-x7）。成对的累积相加结果被加法器17和减法器 18，分别确定元素（x0，x7）。 执行操作的特定次数，其数量是输入数据的矩阵的列的元素数量的一半，以确定输出数据的矩阵的列的元素，并且被执行特定次数 其等于矩阵的行的元素的数量或输入数据，以确定输出数据的矩阵的所有元素。 结果，降低了DCT运算电路的规模，从而降低了功耗。

    Radio communication system and radio-frequency integrated circuit
    4.
    发明申请
    Radio communication system and radio-frequency integrated circuit 审中-公开
    无线电通信系统和射频集成电路

    公开(公告)号：US20050159148A1

    公开(公告)日：2005-07-21

    申请号：US11033384

    申请日：2005-01-12

    申请人： Toshihito Habuka ,  Naoto Inokawa ,  Tatsuji Matsuura ,  Toyokazu Hori ,  Hiroshi Nogami

    发明人： Toshihito Habuka ,  Naoto Inokawa ,  Tatsuji Matsuura ,  Toyokazu Hori ,  Hiroshi Nogami

    IPC分类号： H01Q21/29 ,  H04B7/08 ,  H04B7/26 ,  H04L12/28 ,  H04M1/00 ,  H04W16/28 ,  H04W24/00 ,  H04W88/02 ,  H04Q7/20

    CPC分类号： H04W24/00 ,  H01Q21/29 ,  H04B7/0805 ,  H04B7/0814 ,  H04W88/02

    摘要： In a radio communication system having a plurality of antennas, a reception-system circuit including variable gain amplification circuits for amplifying a signal received from either of the antennas and a frequency conversion circuit for down-converting the received signal to a signal of a lower frequency, and a signal measuring circuit for detecting intensity of the received signal, whereby a signal received by either of the antennas is selected in accordance with a reception state and amplified and demodulated, change rates with time of a signal which is formed by the signal measuring circuit are determined in respect of either of the signals received by the plurality of antennas and a control signal for selecting a reception antenna is generated in accordance with a differences between the change rates.

    摘要翻译： 在具有多个天线的无线电通信系统中，包括用于放大从任一天线接收的信号的可变增益放大电路的接收系统电路和用于将接收信号下变频为较低频率的信号的频率转换电路 以及用于检测接收信号的强度的信号测量电路，由此根据接收状态选择由天线中的任一个接收的信号，并且由信号测量形成的信号随时间变化的放大和解调变化率 根据多个天线接收到的信号之一确定电路，并且根据变化率之间的差异生成用于选择接收天线的控制信号。

    Demodulator circuit, radio communication system and communication semiconductor integrated circuit
    5.
    发明申请
    Demodulator circuit, radio communication system and communication semiconductor integrated circuit 审中-公开
    解调器电路，无线电通信系统和通信半导体集成电路

    公开(公告)号：US20050213689A1

    公开(公告)日：2005-09-29

    申请号：US11037133

    申请日：2005-01-19

    申请人： Keisuke Matsuda ,  Takashi Okubo ,  Toyokazu Hori ,  Kazuyuki Takada

    发明人： Keisuke Matsuda ,  Takashi Okubo ,  Toyokazu Hori ,  Kazuyuki Takada

    IPC分类号： H04J11/00 ,  H04L25/02 ,  H04L27/00 ,  H04L27/14 ,  H04L27/26 ,  H04L27/38

    CPC分类号： H04L27/3809 ,  H04L25/022 ,  H04L25/0228 ,  H04L27/265 ,  H04L27/2657 ,  H04L27/2675 ,  H04L2027/003 ,  H04L2027/0048 ,  H04L2027/0065 ,  H04L2027/0095

    摘要： A communication semiconductor integrated circuit has a demodulator circuit built in a single semiconductor chip. The demodulator circuit is constructed to demodulate a received OFDM-modulated packet signal including a preamble that has two or more fixed-signal sequences, and to have a frequency-error estimating/correcting function that estimates the frequency error of the received signal by using the received preamble and corrects the received signal for the frequency error, a fast Fourier transform function (FFT portion 210) that converts the time-axis information of the corrected received signal to frequency-axis information, a transmission path response estimating/correcting function that estimates the status of the transmission path from the converted signal and corrects the received signal for the transmission path response, and an averaging function that averages the received signal after being corrected for the frequency error so that the averaging can be performed before the fast Fourier transform process.

    摘要翻译： 通信半导体集成电路具有内置在单个半导体芯片中的解调器电路。 解调器电路被构造为解调包括具有两个或多个固定信号序列的前同步码的接收的OFDM调制分组信号，并且具有频率误差估计/校正功能，该频率误差估计/校正功能通过使用 接收到的前同步码并校正频率误差的接收信号，将校正的接收信号的时间轴信息转换为频率轴信息的快速傅里叶变换函数（FFT部分210），估计 来自转换信号的传输路径的状态，并且校正用于传输路径响应的接收信号，以及对经频率误差校正后的接收信号进行平均的平均函数，使得可以在快速傅立叶变换处理之前执行平均 。

    OFDM demodulation method and semiconductor integrated circuit device
    6.
    发明授权
    OFDM demodulation method and semiconductor integrated circuit device 有权
    OFDM解调方法和半导体集成电路器件

    公开(公告)号：US07313125B2

    公开(公告)日：2007-12-25

    申请号：US10809898

    申请日：2004-03-26

    申请人： Toyokazu Hori ,  Hiroshi Nogami ,  Toshihito Habuka ,  Naoto Inokawa ,  Kazuyuki Takada

    发明人： Toyokazu Hori ,  Hiroshi Nogami ,  Toshihito Habuka ,  Naoto Inokawa ,  Kazuyuki Takada

    IPC分类号： H04L5/04 ,  H04L12/26

    CPC分类号： H04L25/061 ,  H04L27/2657 ,  H04L27/2675 ,  H04L27/2679

    摘要： The invention comprises: processing for receiving an OFDM packet having a preamble and the following data transmission symbol, in which packet the subcarrier interval of the preamble is set wider than that of the data transmission symbol; processing for estimating a DC offset occurring at a receiving side by using the received preamble; processing for correcting the DC offset on the received data transmission symbol, according to the estimation result of the DC offset; and processing for demodulating the DC offset corrected data transmission symbol. Thus, it is possible to estimate a DC offset and then correct the DC offset according to the estimated value, in the OFDM packet with no nul symbol defined there.

    摘要翻译： 本发明包括：接收具有前同步码和后续数据传输符号的OFDM分组的处理，其中前导码的子载波间隔被设置为比数据传输符号的子载波间隔宽; 用于通过使用所接收的前导码来估计在接收侧发生的DC偏移的处理; 根据直流偏移的估计结果对接收到的数据传输符号校正直流偏移的处理; 以及用于解调DC偏移校正数据传输符号的处理。 因此，可以估计DC偏移，然后根据估计值在没有nul符号的OFDM分组中校正DC偏移。