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公开(公告)号：US20060087403A1
公开(公告)日：2006-04-27
申请号：US11255244
申请日：2005-10-20
IPC分类号： H04L9/32
CPC分类号： G07C9/00309
摘要： A keyless entry system comprising a transmitter and a receiver. The transmitter increases a first number stored in the volatile memory according to rules, and transmits the first number by radio. The receiver receives the first number, and if the first number is greater than a second number stored in a memory, outputs a signal to indicate being authenticated as correct and updates the second number to the first number. Further, each time increase in the first number becomes a multiple of a predetermined number, the transmitter writes into a non-volatile memory a third number equal to the predetermined number plus the first number. When the first number in the volatile memory is erased due to the exchange, etc., of the battery, the transmitter reads out the third number from the non-volatile memory and writes the third number as the first number into the volatile memory.
摘要翻译： 一种无钥匙进入系统，包括发射机和接收机。 发射机根据规则增加存储在易失性存储器中的第一号码，并通过无线电发送第一号码。 接收器接收第一号码，并且如果第一号码大于存储在存储器中的第二号码，则输出指示正确认证的信号并将第二号码更新为第一号码。 此外，每当第一个数量的每次增加变为预定数量的倍数时，发送器将等于预定数量加上第一个数字的第三个数量写入非易失性存储器。 当由于电池的交换等而使易失性存储器中的第一个数字被擦除时，发送器从非易失性存储器读出第三个数字，并将第三个数字作为第一个数字写入到易失性存储器中。
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公开(公告)号：US07271636B2
公开(公告)日：2007-09-18
申请号：US11163757
申请日：2005-10-28
申请人： Hiroya Yamamoto , Masahiro Umewaka , Shinji Osugi
发明人： Hiroya Yamamoto , Masahiro Umewaka , Shinji Osugi
IPC分类号： H03K3/00
CPC分类号： H03K17/223
摘要： In some examples, a hysteresis comparator includes a series resistor portion including a plurality of resistors for dividing a power supply voltage, the series resistor portion generating a first midpoint voltage and a second midpoint voltage higher than the first midpoint voltage, a first comparator configured to compare the first midpoint voltage and a reference voltage, a second comparator configured to compare the second midpoint voltage and the reference voltage, and a flip-flop having a clock terminal to which an output signal of the first comparator is applied and a reset terminal to which an output signal of the second comparator is applied. In some examples, a hysteresis comparator further includes an OR gate to which output signals of the first comparator and the second comparator are applied, and an AND gate to which output signals of the first comparator and the second comparator are applied.
摘要翻译： 在一些示例中，滞环比较器包括串联电阻器部分，其包括用于分割电源电压的多个电阻器，串联电阻器部分产生第一中点电压和高于第一中点电压的第二中点电压;第一比较器，被配置为 比较第一中点电压和参考电压，配置为比较第二中点电压和参考电压的第二比较器，以及具有施加第一比较器的输出信号的时钟端子的触发器和复位端子 其中施加了第二比较器的输出信号。 在一些示例中，滞环比较器还包括施加第一比较器和第二比较器的输出信号的或门，以及施加第一比较器和第二比较器的输出信号的与门。
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3.发明授权Tuning circuit with amplitude attenuation function and integrated circuit for radio communication apparatus 失效具有振幅衰减功能的调谐电路和无线电通信装置的集成电路公开(公告)号：US07330708B2
公开(公告)日：2008-02-12
申请号：US11001460
申请日：2004-11-30
IPC分类号： H04B1/18
CPC分类号： B60R25/24 , G06K19/0723 , H03J5/246
摘要： There is disclosed a tuning circuit having a coil and a capacitor comprises a resistance-adjustment circuit connected in parallel with the coil and the capacitor. The resistance-adjustment circuit changes a resistance of the tuning circuit when resonant. The resistance-adjustment circuit comprises a series circuit of a resistor and a switching element having an ON-resistance smaller than the resistance of the resistor, and turning on/off the switching element causes the resistance of the tuning circuit when resonant to change.
摘要翻译： 公开了一种具有线圈的调谐电路，并且电容器包括与线圈和电容器并联连接的电阻调节电路。 电阻调节电路在谐振时改变调谐电路的电阻。 电阻调节电路包括电阻器和具有比电阻器的电阻小的导通电阻的开关元件的串联电路，并且开关元件的导通/截止使谐振时的调谐电路的电阻发生变化。
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公开(公告)号：US07386328B2
公开(公告)日：2008-06-10
申请号：US10953373
申请日：2004-09-29
申请人： Masahiro Umewaka , Hiroya Yamamoto
发明人： Masahiro Umewaka , Hiroya Yamamoto
IPC分类号： H04B17/02
CPC分类号： H04B7/0814 , Y02D70/444
摘要： To provide a receiver having a plurality of receiver circuits respectively connected to different antennas and a selecting circuit for selecting a receiver circuit whose receiving level is equal to a predetermined threshold value or a receiver circuit whose receiving level is higher than the predetermined threshold value as a main processing circuit to bring at least some of the receiver circuits other than the selected receiver circuit into a non-operation state.
摘要翻译： 为了提供具有分别连接到不同天线的多个接收机电路的接收机和用于选择其接收电平等于预定阈值的接收机电路的选择电路或接收电平高于预定阈值的接收机电路，作为 主处理电路将除所选接收机电路以外的至少一些接收机电路进入非操作状态。
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5.发明申请Tuning circuit with amplitude attenuation function and integrated circuit for radio communication apparatus 失效具有振幅衰减功能的调谐电路和无线电通信装置的集成电路公开(公告)号：US20050147193A1
公开(公告)日：2005-07-07
申请号：US11001460
申请日：2004-11-30
CPC分类号： B60R25/24 , G06K19/0723 , H03J5/246
摘要： There is disclosed a tuning circuit having a coil and a capacitor comprises a resistance-adjustment circuit connected in parallel with the coil and the capacitor. The resistance-adjustment circuit changes a resistance of the tuning circuit when resonant. The resistance-adjustment circuit comprises a series circuit of a resistor and a switching element having an ON-resistance smaller than the resistance of the resistor, and turning on/off the switching element causes the resistance of the tuning circuit when resonant to change.
摘要翻译： 公开了一种具有线圈的调谐电路，并且电容器包括与线圈和电容器并联连接的电阻调节电路。 电阻调节电路在谐振时改变调谐电路的电阻。 电阻调节电路包括电阻器和具有比电阻器的电阻小的导通电阻的开关元件的串联电路，并且开关元件的导通/截止使谐振时的调谐电路的电阻发生变化。
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公开(公告)号：US07171178B2
公开(公告)日：2007-01-30
申请号：US10763441
申请日：2004-01-23
IPC分类号： H04B1/16
CPC分类号： G06K19/0723
摘要： A tuning circuit having an amplitude-varying function is disclosed that comprises a coil, a capacitor, and a resistance-adjusting element connected in parallel to the coil and the capacitor for varying resistance at time of resonance of the tuning circuit, wherein the amplitude of an output signal of the tuning circuit is varied by varying the resistance with the resistance-adjusting element.
摘要翻译： 公开了一种具有振幅变化功能的调谐电路，其包括与线圈和电容器并联连接的线圈，电容器和电阻器，用于在调谐电路的谐振时改变电阻，其中振幅 通过用电阻调节元件改变电阻来改变调谐电路的输出信号。
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公开(公告)号：US20050070341A1
公开(公告)日：2005-03-31
申请号：US10953373
申请日：2004-09-29
申请人： Masahiro Umewaka , Hiroya Yamamoto
发明人： Masahiro Umewaka , Hiroya Yamamoto
CPC分类号： H04B7/0814 , Y02D70/444
摘要： To provide a receiver having a plurality of receiver circuits respectively connected to different antennas and a selecting circuit for selecting a receiver circuit whose receiving level is equal to a predetermined threshold value or a receiver circuit whose receiving level is higher than the predetermined threshold value as a main processing circuit to bring at least some of the receiver circuits other than the selected receiver circuit into a non-operation state.
摘要翻译： 为了提供具有分别连接到不同天线的多个接收机电路的接收机和用于选择其接收电平等于预定阈值的接收机电路的选择电路或接收电平高于预定阈值的接收机电路，作为 主处理电路将除所选接收机电路以外的至少一些接收机电路进入非操作状态。
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8.发明授权Tone control device and sound volume/tone control device for reducing noise at the time of tone modification 失效音调控制装置和音量/音调控制装置，用于降低音调修改时的噪音
公开(公告)号：US06108428A
公开(公告)日：2000-08-22
申请号：US839013
申请日：1997-04-23
申请人： Masaaki Suzuki , Masahiro Umewaka
发明人： Masaaki Suzuki , Masahiro Umewaka
摘要： A volume/tone control circuit comprises first and second latch circuits (8) and (9) for latching the volume control data BD and the tone control data TD stored in the shift register (7); a volume regulating circuit (2) and a tone regulating circuit (3) for regulating the volume and the tone of the input audio signal according to the respective output data of the first and second latch circuits (8) and (9); and a zero-crossing detection circuit (12) for detecting zero-crossings of the input signal. The input audio signal is fed to the zero-crossing detection circuit (12) when a data detection circuit (20) detects that the input data and the output data of the first latch circuit (8) differ. The output audio signal of the tone regulating circuit is fed to the zero-crossing detection circuit (12) when the input data and the output data of the second latch circuit (9) differ and they control data of either the first latch circuit or the second latch circuit is updated in response to the detection output of the zero-crossing detection circuit.
摘要翻译： 音量/音调控制电路包括用于锁存音量控制数据BD和存储在移位寄存器（7）中的音调控制数据TD）的第一和第二锁存电路（8）和（9）。 音量调节电路（2）和音调调节电路（3），用于根据第一和第二锁存电路（8）和（9）的相应输出数据来调节输入音频信号的音量和音调; 以及用于检测输入信号的过零点的过零检测电路（12）。 当数据检测电路（20）检测到第一锁存电路（8）的输入数据和输出数据不同时，输入音频信号被馈送到过零检测电路（12）。 当输入数据和第二锁存电路（9）的输出数据不同时，音调调节电路的输出音频信号被馈送到过零检测电路（12），并且它们控制第一锁存电路或 响应于过零检测电路的检测输出来更新第二锁存电路。
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公开(公告)号：US20050084041A1
公开(公告)日：2005-04-21
申请号：US10933129
申请日：2004-09-02
申请人： Masahiro Umewaka
发明人： Masahiro Umewaka
IPC分类号： H04L27/14 , H04L25/49 , H04L27/156 , H04L27/26
CPC分类号： H04L25/4902
摘要： A demodulation circuit for demodulating an FSK signal comprising a long bit having a long bit period and a short bit having a short bit period comprises a bit boundary detection section for detecting a bit boundary timing of each bit, and a bit determination section for making determination for each bit such that a particular bit is determined to be a long bit when a threshold time period has passed during a period from a bit boundary timing at a leading end of the bit to a bit boundary timing at a trailing end of the bit, and a particular bit is determined to be a short bit when the threshold time period has not passed during a period from a bit boundary timing at a leading end of the bit to a bit boundary timing at a trailing end of the bit.
摘要翻译： 一种用于解调包括具有长位周期的长位和具有短位周期的短位的FSK信号的解调电路包括用于检测每个位的位边界定时的位边界检测部分，以及用于进行判定的位确定部分 对于每个位，使得当在比特的前端的比特边界定时到比特的后端的比特边界定时的周期期间经过阈值时间周期时，特定比特被确定为长比特， 并且当在比特的前端的比特边界定时到比特的后端的比特边界定时的周期期间没有经过阈值时间周期时，将特定比特确定为短位。
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公开(公告)号：US07369629B2
公开(公告)日：2008-05-06
申请号：US10933129
申请日：2004-09-02
申请人： Masahiro Umewaka
发明人： Masahiro Umewaka
CPC分类号： H04L25/4902
摘要： A demodulation circuit for demodulating an FSK signal comprising a long bit having a long bit period and a short bit having a short bit period comprises a bit boundary detection section for detecting a bit boundary timing of each bit, and a bit determination section for making determination for each bit such that a particular bit is determined to be a long bit when a threshold time period has passed during a period from a bit boundary timing at a leading end of the bit to a bit boundary timing at a trailing end of the bit, and a particular bit is determined to be a short bit when the threshold time period has not passed during a period from a bit boundary timing at a leading end of the bit to a bit boundary timing at a trailing end of the bit.
摘要翻译： 一种用于解调包括具有长位周期的长位和具有短位周期的短位的FSK信号的解调电路包括用于检测每个位的位边界定时的位边界检测部分，以及用于进行判定的位确定部分 对于每个位，使得当在比特的前端的比特边界定时到比特的后端的比特边界定时的周期期间经过阈值时间周期时，特定比特被确定为长比特， 并且当在比特的前端的比特边界定时到比特的后端的比特边界定时的周期期间没有经过阈值时间周期时，将特定比特确定为短位。
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