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    Keyless entry system, transmitter, and receiver
    1.
    发明申请
    Keyless entry system, transmitter, and receiver 审中-公开
    无钥匙进入系统，发射机和接收机

    公开(公告)号：US20060087403A1

    公开(公告)日：2006-04-27

    申请号：US11255244

    申请日：2005-10-20

    申请人： Hiroya Yamamoto ,  Masahiro Umewaka ,  Shinji Osugi ,  Kazumasa Chigira ,  Akira Iketani

    发明人： Hiroya Yamamoto ,  Masahiro Umewaka ,  Shinji Osugi ,  Kazumasa Chigira ,  Akira Iketani

    IPC分类号： H04L9/32

    CPC分类号： G07C9/00309

    摘要： A keyless entry system comprising a transmitter and a receiver. The transmitter increases a first number stored in the volatile memory according to rules, and transmits the first number by radio. The receiver receives the first number, and if the first number is greater than a second number stored in a memory, outputs a signal to indicate being authenticated as correct and updates the second number to the first number. Further, each time increase in the first number becomes a multiple of a predetermined number, the transmitter writes into a non-volatile memory a third number equal to the predetermined number plus the first number. When the first number in the volatile memory is erased due to the exchange, etc., of the battery, the transmitter reads out the third number from the non-volatile memory and writes the third number as the first number into the volatile memory.

    摘要翻译： 一种无钥匙进入系统，包括发射机和接收机。 发射机根据规则增加存储在易失性存储器中的第一号码，并通过无线电发送第一号码。 接收器接收第一号码，并且如果第一号码大于存储在存储器中的第二号码，则输出指示正确认证的信号并将第二号码更新为第一号码。 此外，每当第一个数量的每次增加变为预定数量的倍数时，发送器将等于预定数量加上第一个数字的第三个数量写入非易失性存储器。 当由于电池的交换等而使易失性存储器中的第一个数字被擦除时，发送器从非易失性存储器读出第三个数字，并将第三个数字作为第一个数字写入到易失性存储器中。

    Random Number Generating Circuit
    2.
    发明申请
    Random Number Generating Circuit 审中-公开
    随机数生成电路

    公开(公告)号：US20070067374A1

    公开(公告)日：2007-03-22

    申请号：US11275874

    申请日：2006-02-01

    申请人： Akira Iketani ,  Shizuka Ishimura ,  Kazumasa Chigira

    发明人： Akira Iketani ,  Shizuka Ishimura ,  Kazumasa Chigira

    IPC分类号： G06F7/58

    CPC分类号： G06F7/588 ,  H04L9/06 ,  H04L9/0861

    摘要： A random number generating circuit comprises a pseudo random number generating circuit that generates pseudo random numbers of an M-sequence; a physical random number generating circuit that generates physical random numbers; and a modulation circuit that modulates the physical random numbers generated by the physical random number generating circuit with the use of the pseudo random numbers generated by the pseudo random number generating circuit. The pseudo random number generating circuit can generate pseudo random numbers of a plurality of the M-sequences, and switches the M-sequences generated by the pseudo random number generating circuit based on the physical random numbers generated by the physical random number generating circuit.

    摘要翻译： 一个随机数产生电路包括产生M序列的伪随机数的伪随机数产生电路; 产生物理随机数的物理随机数产生电路; 以及调制电路，其通过使用由伪随机数产生电路产生的伪随机数来调制由物理随机数产生电路产生的物理随机数。 伪随机数发生电路可以生成多个M序列的伪随机数，并且基于由物理随机数产生电路产生的物理随机数来切换由伪随机数产生电路产生的M序列。

    Encryption Processing Circuit
    3.
    发明申请
    Encryption Processing Circuit 审中-公开
    加密处理电路

    公开(公告)号：US20060171532A1

    公开(公告)日：2006-08-03

    申请号：US11275880

    申请日：2006-02-01

    申请人： Akira Iketani ,  Shizuka Ishimura ,  Kazumasa Chigira

    发明人： Akira Iketani ,  Shizuka Ishimura ,  Kazumasa Chigira

    IPC分类号： H04L9/28

    CPC分类号： H04L9/0625 ,  H04L2209/125

    摘要： An encryption processing circuit which performs a permutation process of a common key block encryption system that permutes input data of plural bits according to a per-bit correspondence rule and outputs the processed data. The encryption processing circuit comprises a data input unit that receives the input data of plural bits, the data input unit having an output port that outputs the received input data of plural bits in parallel; a data output unit that has an input port to which data of plural bits is input in parallel, the data output unit outputting the data of plural bits inputted to the input port; and a permuting unit that connects the output port and the input port according to the per-bit correspondence rule.

    摘要翻译： 一种加密处理电路，其执行公共密钥块加密系统的置换处理，该公共密钥块加密系统根据每比特对应规则对多个比特的输入数据进行排列，并输出经处理的数据。 加密处理电路包括接收多个比特的输入数据的数据输入单元，数据输入单元具有输出端口，并行输出多个比特的接收输入数据; 数据输出单元，其输入并行输入多位的数据的输入端口，所述数据输出单元输出输入到所述输入端口的多位数据; 以及根据每位对应规则连接输出端口和输入端口的置换单元。

    Semiconductor laser device and semiconductor laser module using the same
    4.
    发明授权
    Semiconductor laser device and semiconductor laser module using the same 有权
    半导体激光器件和半导体激光器模块使用相同

    公开(公告)号：US06567447B1

    公开(公告)日：2003-05-20

    申请号：US09680153

    申请日：2000-10-03

    申请人： Junji Yoshida ,  Naoki Tsukiji ,  Akira Iketani ,  Naoki Kimura ,  Jun Niekawa ,  Toshio Kimura ,  Takeshi Aikiyo

    发明人： Junji Yoshida ,  Naoki Tsukiji ,  Akira Iketani ,  Naoki Kimura ,  Jun Niekawa ,  Toshio Kimura ,  Takeshi Aikiyo

    IPC分类号： H01S500

    CPC分类号： H01S5/34 ,  B82Y20/00 ,  H01S5/02216 ,  H01S5/02284 ,  H01S5/02415 ,  H01S5/02492 ,  H01S5/028 ,  H01S5/1039 ,  H01S5/146 ,  H01S5/3403

    摘要： In the semiconductor laser device of the present invention, a semiconductor stacked structure including an active layer comprising a strained multi-quantum well structure is formed on a substrate 1, a cavity length is larger than 1000 &mgr;m but equal to or smaller than 1800 &mgr;m, and a low-reflection film S1 having a reflectance of 3% or less is formed on one facet and a high-reflection film S2 having a reflectance of 90% or more is formed on the other facet. The semiconductor laser module has a structure in which the semiconductor laser device is set to a cooling device constituted by electrically alternately arranging 40 pairs or more of the Peltier elements and holding them by top and bottom ceramic plates and sealed in the package. A grating having a reflection bandwidth of 1.5 nm or less is formed on an optical fiber to be built in.

    摘要翻译： 在本发明的半导体激光装置中，在基板1上形成包括应变多量子阱结构的有源层的半导体层叠结构，空洞长度大于1000μm，但等于或小于1800μm， 并且在一个面上形成反射率为3％以下的低反射膜S1，另一方面形成反射率为90％以上的高反射膜S2。 半导体激光器模块具有这样的结构，其中半导体激光器件被设置为通过电气交替地布置40对或更多个珀耳帖元件并由顶部和底部陶瓷板保持并且密封在封装中的冷却装置。 在内置的光纤上形成具有1.5nm以下的反射带宽的光栅。

    Apparatus and method for recording and reproducing digital signal in synchronization blocks
    8.
    发明授权
    Apparatus and method for recording and reproducing digital signal in synchronization blocks 失效
    用于在同步块中记录和再现数字信号的装置和方法

    公开(公告)号：US5655050A

    公开(公告)日：1997-08-05

    申请号：US659623

    申请日：1996-06-06

    申请人： Yoshiki Yamamoto ,  Tetsuya Mizushima ,  Akira Iketani ,  Yasunori Kawakami ,  Chiyoko Matsumi

    发明人： Yoshiki Yamamoto ,  Tetsuya Mizushima ,  Akira Iketani ,  Yasunori Kawakami ,  Chiyoko Matsumi

    IPC分类号： G11B20/12 ,  G11B5/008 ,  G11B5/09 ,  G11B20/18 ,  G11B27/28 ,  G11B27/30 ,  H04N5/926 ,  H04N5/935 ,  H04N5/945 ,  H04N5/76

    CPC分类号： G11B20/1208 ,  G11B27/3027 ,  H04N5/9261 ,  H04N5/935 ,  G11B20/1833 ,  G11B2220/90 ,  G11B5/0086 ,  G11B5/09 ,  H04N5/945

    摘要： A digital signal recording apparatus for recording digital signal in synchronization blocks includes a generator for generating a synchronization pattern for indicating the beginning of each synchronization block, a generator for generating an ID data for indicating the sequence of the synchronization blocks, a generator for generating an ID parity for checking the ID data, a generator for generating additional information signal, which is a track width data, a generator for generating audio and video signals. Above data are applied to a pattern generator for generating track data comprising plural consecutive normal synchronization blocks immediately preceded by two mini-synchronization blocks and immediately followed by one mini-synchronization block. Each mini-synchronization block includes the synchrionization pattern, ID data, ID parity, and additional information signal. Each normal synchronization block includes the synchronization pattern, ID data, ID parity, and audio and video signal.

    摘要翻译： 用于在同步块中记录数字信号的数字信号记录装置包括用于产生用于指示每个同步块的开始的同步模式的发生器，用于产生用于指示同步块的序列的ID数据的发生器，用于生成 用于检查ID数据的ID奇偶校验，用于产生作为轨道宽度数据的附加信息信号的发生器，用于产生音频和视频信号的发生器。 上述数据被应用于模式发生器，用于产生包括紧接在两个小型同步块之前的多个连续正常同步块的跟踪数据，并且紧随其后的是一个小型同步块。 每个小型同步块包括同步模式，ID数据，ID奇偶校验和附加信息信号。 每个正常同步块包括同步模式，ID数据，ID奇偶校验以及音频和视频信号。

    Data transmitter, data receiver, processor, equipment managing device, equipment managing system, data transmitting-receiving system, and medium
    10.
    发明授权
    Data transmitter, data receiver, processor, equipment managing device, equipment managing system, data transmitting-receiving system, and medium 失效
    数据发送器，数据接收器，处理器，设备管理装置，设备管理系统，数据发送接收系统和介质

    公开(公告)号：US06532269B2

    公开(公告)日：2003-03-11

    申请号：US09230995

    申请日：1999-02-05

    申请人： Masazumi Yamada ,  Akira Iketani ,  Akira Usui ,  Masaaki Kobayashi ,  Hidetoshi Takeda

    发明人： Masazumi Yamada ,  Akira Iketani ,  Akira Usui ,  Masaaki Kobayashi ,  Hidetoshi Takeda

    IPC分类号： H04N327

    CPC分类号： H04N19/10 ,  H04N21/4325 ,  H04N21/43632

    摘要： When transmitting encoded video data and audio data, a transmitter 201 also transmits a decoding method 107 generated by decoding-method generation means 203. In the case of a receiver 202, decoding control means 111 controls decoding means 208 in accordance with a received decoding method 113 and thereby, decodes video data and audio data 115. Thus, it is unnecessary for the receiver 202 to previously prepare all of a plurality of decoding methods and the transmitter 201 does not need to encode video data or audio data in accordance with the decoding method owned by the receiver 202.

    摘要翻译： 当发送编码视频数据和音频数据时，发送器201还发送由解码方法生成装置203生成的解码方法107.在接收机202的情况下，解码控制装置111根据接收到的解码方法控制解码装置208 113，从而对视频数据和音频数据115进行解码。因此，接收机202不需要预先准备多种解码方法，并且发射机201不需要根据解码对视频数据或音频数据进行编码 方法由接收机202拥有。