公开(公告)号：US20130058643A1

公开(公告)日：2013-03-07

申请号：US13665146

申请日：2012-10-31

申请人： Hiroyuki HONMA ,  Toru Katagiri ,  Hiromichi Makishima ,  Masahiro Shioda ,  Hiroyuki Kitajima ,  Ichiro Yokokura

发明人： Hiroyuki HONMA ,  Toru Katagiri ,  Hiromichi Makishima ,  Masahiro Shioda ,  Hiroyuki Kitajima ,  Ichiro Yokokura

IPC分类号： H04B10/08

CPC分类号： H04J3/1652 ,  H04J2203/0058 ,  H04L43/0876

摘要： A data amount derivation apparatus includes: a first calculator configured to derive, for one series of parallelized mapping signals, amount of data in each frame period for a frame into which the parallelized mapping signals are mapped; and a second calculator configured to sum up amounts of data in N frame periods, where N is an integer, and to derive the resulting summation value as the amount of data to be mapped into the frame, each of the amounts of data in each of the frame periods being derived by the first calculator.

摘要翻译： 数据量导出装置包括：第一计算器，被配置为针对一系列并行映射信号，对并行映射信号映射到的帧的每个帧周期中的数据量; 以及第二计算器，被配置为对N个帧周期内的数据量进行相加，其中N是整数，并且导出所得到的求和值作为要映射到该帧中的数据量，每个数据量 帧周期由第一计算器导出。

公开(公告)号：US08300660B2

公开(公告)日：2012-10-30

申请号：US12697245

申请日：2010-01-30

申请人： Ichiro Yokokura ,  Hiromichi Makishima ,  Shinji Sawane

发明人： Ichiro Yokokura ,  Hiromichi Makishima ,  Shinji Sawane

IPC分类号： H04J3/22

CPC分类号： H04J3/0623

摘要： A transmitting apparatus includes a detecting unit that detects deviation and balance relative to a specified bit rate of a frame signal input at a constant bit rate; a dividing unit that reads at constant intervals from a buffer storing the frame signal and outputs a signal divided into a plurality of segments having a predetermined data length; and a correcting unit that, based on the deviation and balance detected by the detecting unit, corrects the data length for the division by the dividing unit.

摘要翻译： 发送装置包括检测单元，其检测相对于以恒定比特率输入的帧信号的指定比特率的偏差和平衡; 分割单元，从存储帧信号的缓冲器以恒定的间隔读取，并输出分割成具有预定数据长度的多个段的信号; 以及校正单元，其基于由所述检测单元检测到的偏差和平衡来校正由所述分割单元划分的数据长度。

公开(公告)号：US07397882B2

公开(公告)日：2008-07-08

申请号：US10671593

申请日：2003-09-29

申请人： Ichiro Yokokura ,  Yuji Obana ,  Hideaki Mochizuki

发明人： Ichiro Yokokura ,  Yuji Obana ,  Hideaki Mochizuki

IPC分类号： H03D3/24

CPC分类号： H03L7/0993 ,  H03L7/107 ,  H04J3/076

摘要： A digital phase locked circuit provides an output clock signal whose phase is synchronous with the phase of an input clock signal under a desired level of a phase absorption characteristic even if the input clock signal is supplied in a burst fashion. A phase comparing part compares the phase of the output clock signal with the phase of the input clock signal. A phase comparison result detecting part outputs an INC/DEC request signal for controlling a division operation based on a phase comparison signal. An execution rate computing part computes a phase difference between the input clock signal and the output clock signal based on the INC/DEC request signal and outputs an execution rate corresponding to the phase difference. A clock generating part controls a division operation for the master clock signal in accordance with the INC/DEC request signal and changes phase absorption speed of the output clock signal in accordance with the execution rate.

摘要翻译： 数字锁相电路提供输出时钟信号，其输出时钟信号的相位与期望的相位吸收特性水平下的输入时钟信号的相位同步，即使以突发方式提供输入时钟信号。 相位比较部分将输出时钟信号的相位与输入时钟信号的相位进行比较。 相位比较结果检测部分输出用于根据相位比较信号控制除法运算的INC / DEC请求信号。 执行率计算部分根据INC / DEC请求信号计算输入时钟信号和输出时钟信号之间的相位差，并输出与相位差对应的执行速率。 时钟产生部分根据INC / DEC请求信号控制主时钟信号的除法运算，并根据执行速率改变输出时钟信号的相位吸收速度。