公开(公告)号：US08724659B2

公开(公告)日：2014-05-13

申请号：US11913778

申请日：2005-05-11

Applicant: Tore Andre ,  Anders Lindblad ,  Kenneth Johansson

Inventor： Tore Andre ,  Anders Lindblad ,  Kenneth Johansson

IPC: H04J3/06 ,  H04L7/04

CPC classification number: H03L7/091 ,  H03L7/0993 ,  H03L7/181 ,  H04J3/0632 ,  H04J3/0664 ,  H04J3/0697 ,  H04Q2213/13039 ,  H04Q2213/13199 ,  H04Q2213/13214 ,  H04Q2213/13292 ,  H04Q2213/13297 ,  H04Q2213/13298 ,  H04Q2213/1336 ,  H04Q2213/13389

Abstract: A packet forwarding unit such as a Digital Subscriber Line Access Multiplexer (DSLAM) receives Ethernet packets carrying real-time information and forwards the information therein on output lines such as Asymmetric Digital Subscriber Lines (ADSLs). The DSLAM includes a clock device having an extraction unit and an adaptive clock. The extraction unit analyzes received packets to select streams of received packets from one destination to one user, and the adaptive clock generates a reference clock signal according to the arrival times of packets in the selected streams. The clock signal is sent to time reference units in DSL modems for the output lines.

Abstract translation: 诸如数字用户线路接入复用器（DSLAM）的分组转发单元接收携带实时信息的以太网分组，并在诸如非对称数字用户线路（ADSL）的输出线路上转发该信息。 DSLAM包括具有提取单元和自适应时钟的时钟设备。 提取单元分析接收到的分组以选择从一个目的地到一个用户的接收分组的流，并且自适应时钟根据所选择的分组中的分组的到达时间生成参考时钟信号。 时钟信号被发送到用于输出线路的DSL调制解调器中的时间参考单元。

公开(公告)号：US06380776B1

公开(公告)日：2002-04-30

申请号：US09934287

申请日：2001-08-21

Applicant: Robert L. Yocom

Inventor： Robert L. Yocom

IPC: H03L700

CPC classification number: H03L7/091 ,  H03L7/0993

Abstract: Digital circuitry synchronizes clock signals in a digital circuit. A value of a reference clock is sampled at a plurality of points near a transition point of a generated clock. It is determined whether the reference clock transitioned from a first state to a second state before, after or within an acceptable range of a transition point of the generated clock. Upon determining that the reference clock transitioned before the transition point of the generated clock, one period of the generated clock is shortened. Upon determining that the reference clock transitioned after the transition point of the generated clock, one period of the generated clock is lengthened.

Abstract translation: 数字电路同步数字电路中的时钟信号。 在生成的时钟的转变点附近的多个点处对参考时钟的值进行采样。 确定参考时钟是否在所产生的时钟的转换点的可接受范围之前，之后或之内从第一状态转换到第二状态。 在确定参考时钟在生成的时钟的转变点之前转变时，产生的时钟的一个周期被缩短。 在确定参考时钟在所产生的时钟的转变点之后转变时，产生的时钟的一个周期被延长。

公开(公告)号：US5914991A

公开(公告)日：1999-06-22

申请号：US884857

申请日：1997-06-30

Applicant: Scott Gigandet ,  John F. Sullivan ,  Robert Addiss

Inventor： Scott Gigandet ,  John F. Sullivan ,  Robert Addiss

IPC: G06F3/05 ,  A61B5/00 ,  A61B5/0408 ,  H03L7/099 ,  H04L7/00 ,  H04L7/033

CPC classification number: H03L7/0993 ,  A61B5/0002 ,  A61B5/04085 ,  A61B5/1455 ,  H04L7/0083 ,  H04L7/0331

Abstract: Apparatus for synchronizing a reference clock signal received from a host system with an A/D converter clock signal generated in a data acquisition pod. The pod includes a decoder responsive to communication received from the host for extracting a host reference signal, and a clock signal source for developing an A/D reference clock signal having a frequency that is different from the frequency of the host reference signal. A pulse modifying digital phase-locked loop (PLL) is responsive to the A/D reference clock signal and the host reference signal for developing an A/D clock signal for an A/D converter in which one of its clock periods is periodically modified, thereby locking the rate at which the A/D converter develops samples to the rate at which the host system requests samples. In a preferred embodiment the pod also includes a signal detector for detecting a specified alignment in time of the readiness of the A/D converter to provide a given sample with a host system request for that given sample, and upon such detection, selectively providing an enable signal to the PLL, thereby enabling operation of the PLL and synchronizing the host and pod clock rates, as well as locking in a given alignment the providing to the host of the samples developed by the A/D converter with the host system requests for those samples.

Abstract translation: 用于使从主机系统接收的参考时钟信号与在数据采集盒中产生的A / D转换器时钟信号同步的装置。 盒包括响应于从主机接收的用于提取主机参考信号的通信的解码器，以及用于开发具有与主机参考信号的频率不同的频率的A / D参考时钟信号的时钟信号源。 脉冲修改数字锁相环（PLL）响应于A / D参考时钟信号和主机参考信号，用于开发用于A / D转换器的A / D时钟信号，其中周期性修改其一个时钟周期 ，从而将A / D转换器开发采样的速率锁定到主机系统请求采样的速率。 在优选实施例中，盒还包括信号检测器，用于在A / D转换器准备就绪时检测指定的对准，以向给定采样提供对该给定采样的主机系统请求，并且在这种检测时，选择性地提供 使能信号到PLL，从而使得PLL的操作和主机和pod时钟速率的同步，以及在给定的对准中锁定向A / D转换器开发的样本的主机提供主机系统请求 那些样品。

公开(公告)号：US5577080A

公开(公告)日：1996-11-19

申请号：US201644

申请日：1994-02-25

Applicant: Kenji Sakaue ,  Koji Ogura

Inventor： Kenji Sakaue ,  Koji Ogura

IPC: H03L7/06 ,  H03L7/091 ,  H03L7/099 ,  H03L7/107 ,  H03D3/24

CPC classification number: H03L7/0993 ,  H03L7/091 ,  H03L7/107

Abstract: A digital phase-locked loop (DPLL) circuit, which achieves a high-precise phase matching between input and output clocks at high speed, irrespective of phase difference between both, is disclosed. The DPLL has a phase comparator for sequentially comparing an input clock with an output clock in phase and outputting phase comparison result signals; a random walk filter for sequentially adding and accumulating the comparison result signals inputted by the phase comparator, discriminating a relative magnitude between the obtained addition data and threshold value information, and outputting a frequency change signal corresponding to the discriminated result and the phase shift amount information; a variable frequency oscillator for generating the output clock and changing frequency of the output clock according to the frequency change signal; and a filter coefficient generating circuit for changing and outputting at least one of the outputted threshold value information and the phase shift amount information according to the phase synchronous status supplied from an operation status detecting circuit.

Abstract translation: 公开了一种数字锁相环（DPLL）电路，其在高速下实现了输入和输出时钟之间的高精度相位匹配，而不考虑两者之间的相位差。 DPLL具有相位比较器，用于顺序地将输入时钟与输出时钟同相比较并输出相位比较结果信号; 随机游走滤波器，用于顺序地相加和累加由相位比较器输入的比较结果信号，鉴别所获得的相加数据与阈值信息之间的相对幅度，并输出与鉴别结果和相移量信息相对应的频率变化信号 ; 可变频率振荡器，用于根据频率变化信号产生输出时钟并改变输出时钟的频率; 以及滤波器系数发生电路，用于根据从操作状态检测电路提供的相位同步状态来改变和输出输出的阈值信息和相移量信息中的至少一个。

公开(公告)号：US5025461A

公开(公告)日：1991-06-18

申请号：US362802

申请日：1989-06-05

Applicant: Dieter Pauer

Inventor： Dieter Pauer

IPC: H04L7/02 ,  H03L7/099 ,  H04L7/033

CPC classification number: H04L7/0331 ,  H03L7/0993

Abstract: A local bit clock having the frequency of the signal to be received is generated at the receiving end by means of a clock generator (TG) and a counter (Z). A phase evaluation logic (PAL) evaluates the time position of the leading edge of a received pulse in comparison with a predetermined time position of the effective pulse edge of the local bit clock. In the synchronous case, the effective pulse edge is located at the center of the received pulse (center-of-bit sampling). Because of nonideal line properties, the duration of the received pulses may differ from the desired value. To be able to distinguish a momentary edge drift of a received pulse (pulse too short or too long) from an actual phase shift, the time positions of the leading and trailing edges of each pulse are determined. If a pulse is too short or too long but symmetrical with respect to the predetermined time position of the effective pulse edge of the local bit clock, this indicates a momentary edge drift, so that no phase correction is necessary.

Abstract translation: 在接收端通过时钟发生器（TG）和计数器（Z）产生具有要接收的信号频率的本地位时钟。 相位评估逻辑（PAL）与本地位时钟的有效脉冲边沿的预定时间位置相比较，评估接收脉冲前沿的时间位置。 在同步情况下，有效脉冲边沿位于接收脉冲的中心（中心位采样）。 由于非线性特性，接收脉冲的持续时间可能与期望值不同。 为了能够将接收到的脉冲（脉冲太短或太长）的瞬时边缘漂移与实际相移区分开，确定每个脉冲的前沿和后沿的时间位置。 如果脉冲太短或太长但相对于局部位时钟的有效脉冲边沿的预定时间位置对称，则这表示瞬时边缘漂移，因此不需要相位校正。

公开(公告)号：US4668917A

公开(公告)日：1987-05-26

申请号：US843875

申请日：1986-03-26

Applicant: Stephen N. Levine

Inventor： Stephen N. Levine

IPC: H03K23/66 ,  H03L7/099 ,  H04L7/033 ,  H03K9/06 ,  H03K5/13

CPC classification number: H03L7/0993 ,  H03K23/662 ,  H04L7/0331

Abstract: A phase comparator circuit for use with a digital phase-locked loop which can be programmably altered to provide phase comparisons either on the leading edge or leading and trailing edges of the phase-locked loop output signal, to provide an increased operating bandwidth capability to the phase comparator circuit. The phase comparator circuit can be configured to cooperate with a multiple frequency digital phase-locked loop such that the results of a phase comparison will be delayed until a frequency adjustment has been completed.

Abstract translation: 一种与数字锁相环一起使用的相位比较器电路，其可编程地改变以在锁相环输出信号的前沿或前沿和后沿提供相位比较，以提供增加的工作带宽能力 相位比较电路。 相位比较器电路可以被配置为与多频数字锁相环配合，使得相位比较的结果将被延迟直到频率调整完成。

公开(公告)号：US4573017A

公开(公告)日：1986-02-25

申请号：US567724

申请日：1984-01-03

Applicant: Stephen N. Levine

Inventor： Stephen N. Levine

IPC: H03K23/66 ,  H03L7/099 ,  H04L7/033 ,  H03K5/13 ,  H03K5/22 ,  H03D13/00

CPC classification number: H03L7/0993 ,  H03K23/662 ,  H04L7/0331

Abstract: A unitary phase and frequency adjust network for use in a multiple frequency digital phase-locked loop circuit is described. The unitary phase and frequency adjust network utilizes a single circuit to effect both phase and frequency adjustments. The multiple frequency digital phase-locked loop effects phase adjustments by selectively combining or subtracting a reference clock signal with a derived programmable clock signal thereby generating a composite digital phase-locked loop clock signal. The phase and frequency adjust network effects frequency shifts by selectively adding or subtracting pulses from the composite clock signal at a rate determined by a programmably controlled clock signal.

Abstract translation: 描述了用于多频数字锁相环电路的单相相位调频网络。 单相相位和频率调整网络使用单个电路来实现相位和频率调整。 多频数字锁相环通过选择性地组合或减去参考时钟信号与导出的可编程时钟信号来实现相位调整，从而产生复合数字锁相环时钟信号。 相位和频率调整网络通过以由可编程控制的时钟信号确定的速率选择性地从复合时钟信号中增加或减去脉冲来影响频移。

公开(公告)号：US3578956A

公开(公告)日：1971-05-18

申请号：US3578956D

申请日：1969-05-13

Applicant: ALLEN BRADLEY CO

Inventor： MCCALL AMIEL J

IPC: G05B19/25 ,  H03L7/087 ,  H03L7/099 ,  G06M3/08

CPC classification number: H03L7/087 ,  G05B19/25 ,  H03L7/0993

Abstract: A digital system controls the relative phase of the outputs of two dynamic counters by modulating the input train of pulses to one counter until the two counters are accurately in phase. In the system, successively releasable coarse, medium, and fine inphase detectors, operating at successively higher frequencies, are employed to permit modulation to occur until the desired inphase accuracy is obtained. The coarse in-phase detector first detects an in-phase condition causing release of the medium inphase detector, which next detects an in-phase condition causing release of the fine in-phase detector which provides the final in-phase detection that terminates the modulation. During the entire modulation period, a lead-lag detector controls the direction in which the input train of pulses to the one counter is modulated.

公开(公告)号：US20180095119A1

公开(公告)日：2018-04-05

申请号：US15284374

申请日：2016-10-03

Applicant: Analog Devices Global

Inventor： Vamshi Krishna Chillara ,  Pablo Cruz Dato ,  Declan M. Dalton

IPC: G01R23/02 ,  H03L7/099 ,  H03L7/091 ,  H03L7/107

CPC classification number: G01R23/02 ,  H03L7/08 ,  H03L7/091 ,  H03L7/0993 ,  H03L7/1075 ,  H03L2207/50

Abstract: A chip includes a phase-locked loop (PLL) and a test controller. The PLL includes an oscillator and a phase detector. In a normal mode, a first feedback loop includes a phase detector and an oscillator that generates an output based on a frequency input signal. In a test mode, the PLL is re-configured. The output of the loop filter can be decoupled from the input of the oscillator in the test mode and instead be coupled to the input of the phase detector. The oscillator can receive a test tuning signal provided by the test controller. In this test mode configuration, the PLL can measure the frequency of the oscillator.

公开(公告)号：US09484938B2

公开(公告)日：2016-11-01

申请号：US14486927

申请日：2014-09-15

Applicant: Intel Corporation

Inventor： Martin Vandepas

IPC: H03L7/06 ,  H03L7/099 ,  H03L1/02 ,  H03L7/08

CPC classification number: H03L7/0993 ,  H03L1/02 ,  H03L1/022 ,  H03L7/0802 ,  H03L2207/50

Abstract: Described herein are apparatus, system, and method for controlling temperature drift and/or voltage supply drift in a digital phase locked loop (DPLL). The apparatus comprises a DPLL including a digital filter to generate a fine code for controlling a frequency of an output signal of a digital controlled oscillator (DCO) of the DPLL; a logic unit to monitor the fine code and to generate a compensation signal based on the fine code; and a voltage adjustment unit to update a power supply level to the DCO based on the compensation signal, wherein the updated power supply level to cause the digital filter to generate the fine code near the middle of an entire range of the fine code across various temperatures, and wherein the digital filter to generate the fine code near the middle of the entire range across power supply drift.

Abstract translation: 这里描述了用于控制数字锁相环（DPLL）中的温度漂移和/或电压漂移的装置，系统和方法。 该装置包括一个包括数字滤波器的DPLL，以产生用于控制DPLL的数字控制振荡器（DCO）的输出信号的频率的精细代码; 逻辑单元，用于监视精细代码并基于精细代码产生补偿信号; 以及电压调整单元，用于基于所述补偿信号来更新对所述DCO的电源电平，其中所述更新的电源电平使得所述数字滤波器在各种温度下的所述精细代码的整个范围的中间附近生成所述精细代码 ，并且其中所述数字滤波器用于在电源漂移之间的整个范围的中间附近产生精细代码。