-
公开(公告)号：US20050213967A1
公开(公告)日：2005-09-29
申请号：US10915568
申请日：2004-08-11
IPC分类号： H04B10/27 , H04B10/077 , H04B10/079 , H04B10/29 , H04B10/299 , H04J14/00 , H04J14/02 , H04L12/701 , H04B10/08
CPC分类号： H04J14/0227 , H04J14/0212 , H04J14/0217 , H04J14/0241 , H04J14/028
摘要： If wavelengths λa and λb are dropped in NE (Network Equipment) 2 and a wavelength λc is made Through, and all of wavelengths are made Through in NE3 in a certain time period, a route from NE1 to NE2, a route from NE2 to NE4, and a route from NE1 to NE4 are established. If a user who uses the wavelength λa from NE1 to NE2, and a user who uses the wavelength λb from NE2 to NE4 do not use the routes in another time period, and if another user desires to use a route from NE1 to NE3 and a route from NE3 to NE4, the routes are reestablished in a way such that the wavelength λa is converted into the wavelength λb and made Through in NE2, and the wavelength λb is dropped and added in NE3.
摘要翻译： 如果在NE（网络设备）2中波长λa和lambdab被丢弃，并且波长为lambdac，则所有波长在NE 3中在一定时间内通过，从NE 1到NE 2的路由， NE 2〜NE 4，从NE 1到NE 4的路由建立。 如果使用从NE 1到NE 2的波长λa的用户，以及使用从NE2到NE4的波长lambdab的用户在另一个时间段内不使用路由，并且如果另一个用户期望使用来自NE的路由 1到NE 3，从NE 3到NE 4的路由，重新建立路由，使得波长λa被转换成波长lambdab并在NE2中通过，波长lambdab被丢弃并添加到NE 3中 。
-
公开(公告)号：US20060242463A1
公开(公告)日：2006-10-26
申请号：US11207831
申请日：2005-08-22
IPC分类号： G06F11/00
CPC分类号： G01R31/3004
摘要： An abnormality in operation is detected by meticulously monitoring the operation of a monitored device that comprises a state machine. The state number, indicating the state the monitored device is currently in, is output from the device. The upper and lower limit values of current consumption is set for each state number. A monitoring circuit, using the upper and lower limit values for the present state number, judges the value of current consumption detected by a current detection circuit and detects whether there is abnormality in operation.
摘要翻译： 通过认真监视包括状态机的被监视设备的操作来检测操作异常。 指示被监视设备当前处于的状态的状态号从设备输出。 电流消耗的上下限值为每个状态数设定。 使用当前状态数的上限值和下限值的监视电路，判断由电流检测电路检测出的电流消耗的值，并检测是否存在操作异常。
-
公开(公告)号：US07796050B2
公开(公告)日：2010-09-14
申请号：US11207831
申请日：2005-08-22
IPC分类号： G08B21/00
CPC分类号： G01R31/3004
摘要： An abnormality in operation is detected by meticulously monitoring the operation of a monitored device that comprises a state machine. The state number, indicating the state the monitored device is currently in, is output from the device. The upper and lower limit values of current consumption is set for each state number. A monitoring circuit, using the upper and lower limit values for the present state number, judges the value of current consumption detected by a current detection circuit and detects whether there is abnormality in operation.
摘要翻译： 通过认真监视包括状态机的被监视设备的操作来检测操作异常。 指示被监视设备当前处于的状态的状态号从设备输出。 电流消耗的上下限值为每个状态数设定。 使用当前状态数的上限值和下限值的监视电路，判断由电流检测电路检测出的电流消耗的值，并检测是否存在操作异常。
-
公开(公告)号：US06400614B1
公开(公告)日：2002-06-04
申请号：US09903004
申请日：2001-07-11
申请人： Masaki Hiromori , Seiji Matsuzaki , Toshiaki Asai , Yoshinari Oshio , Masato Hashizume , Megumi Shibata , Yuji Kamura
发明人： Masaki Hiromori , Seiji Matsuzaki , Toshiaki Asai , Yoshinari Oshio , Masato Hashizume , Megumi Shibata , Yuji Kamura
IPC分类号： G11C700
CPC分类号： G06F5/12
摘要： A transmission device and an integrated circuit improved in quality and reliability of digital transmission control. A memory stores an input signal, write address generating means generates a write address for writing in the memory, and read address generating means generates a read address for reading from the memory. Phase state monitoring means monitors a transition from a steady phase state in which writing/reading in/from the memory is normally performed or from a startup state to a coincident phase state in which address values of the write and read addresses coincide with each other or to an unstable phase state in which a phase fluctuation margin is one-sided. When the coincident phase state or the unstable phase state is detected, reset signal output means outputs a reset signal to the write and read address generating means such that the phase relation between the write and read addresses is brought to an optimum phase relation.
摘要翻译： 一种传输设备和集成电路，提高了数字传输控制的质量和可靠性。 存储器存储输入信号，写入地址产生装置产生用于在存储器中写入的写入地址，并且读取地址产生装置产生用于从存储器读取的读取地址。 相位状态监视装置监视从正常执行存储器/从存储器的写入/读取或从启动状态到写入和读取地址的地址值彼此一致的一致相位状态的稳定相位状态的转变，或者 到相位波动幅度是单向的不稳定相位状态。 当检测到重合相位状态或不稳定相位状态时，复位信号输出装置向写和读地址产生装置输出复位信号，使得写入和读出地址之间的相位关系达到最佳相位关系。
-
公开(公告)号：US20090249107A1
公开(公告)日：2009-10-01
申请号：US12368715
申请日：2009-02-10
申请人： Tatsuya Oku , Masato Hashizume , Hiroshi Nishida
发明人： Tatsuya Oku , Masato Hashizume , Hiroshi Nishida
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： A communication apparatus having a clock interface unit supplying a clock signal for synchronization, includes a clock extracting section for extracting a clock component from a receive signal, a decoding section for generating a decoded signal by decoding in a predetermined encoding form the clock component extracted by the clock extracting section, a frame converting section for creating a receive frame by converting the decoded signal to a frame in a predetermined frame form, a determining section for determining whether the predetermined encoding form and the predetermined frame form are right or not on a basis of the receive frame, a setting section for performing setting regarding the clock signal on a basis of the encoding form and frame form determined to be right by the determining section, and a clock signal output section for outputting the clock signal generated on a basis of the setting by the setting section.
摘要翻译： 具有提供用于同步的时钟信号的时钟接口单元的通信装置包括：时钟提取部分，用于从接收信号中提取时钟分量;解码部分，用于通过以预定的编码形式解码解码信号，由时钟分量提取时钟分量， 时钟提取部分，用于通过将解码信号转换为预定帧形式的帧来创建接收帧的帧转换部分，用于基于所述确定部分确定预定编码形式和预定帧形式是否是正确的 一个设置部分，用于根据由确定部分确定为正确的编码形式和帧形式来执行关于时钟信号的设置;以及时钟信号输出部分，用于输出基于 由设置部分设置。
-
公开(公告)号：US08184665B2
公开(公告)日：2012-05-22
申请号：US12627017
申请日：2009-11-30
申请人： Tatsuya Oku , Yasuo Takami , Masato Hashizume
发明人： Tatsuya Oku , Yasuo Takami , Masato Hashizume
IPC分类号： H04J3/06
CPC分类号： H04J3/0688 , H04J3/0691 , H04J3/0697 , H04J2203/006
摘要： A disclosed network device includes a plurality of interface cards that receive clock signals and clock signal quality information from other devices via communication lines, respectively being predetermined communication line types corresponding to the plurality of interface cards, a controller that acquires the clock signal quality information and determines one of the clock signals having a highest quality based on this, and a clock processor that generates a synchronization clock signal used for network synchronization the clock processor, based on the determined one of the clock signals, whereby the clock processor includes a frequency measuring instrument that measures a frequency component of the one of the clock signals, and determines the communication line type corresponding to one of the interface cards, and a clock controller that provides a coefficient to a digital filter based on the determined communication line type.
摘要翻译： 所公开的网络设备包括多个接口卡，其经由通信线路从其他设备接收时钟信号和时钟信号质量信息，分别是对应于多个接口卡的预定通信线路类型，获取时钟信号质量信息的控制器和 基于此确定具有最高质量的时钟信号中的一个;以及时钟处理器，其基于所确定的一个时钟信号，生成用于网络同步时钟处理器的同步时钟信号，由此时钟处理器包括频率测量 测量时钟信号之一的频率分量的仪器，并确定与一个接口卡相对应的通信线路类型;以及时钟控制器，其基于所确定的通信线路类型向数字滤波器提供系数。
-
公开(公告)号：US08321715B2
公开(公告)日：2012-11-27
申请号：US12368715
申请日：2009-02-10
申请人： Tatsuya Oku , Masato Hashizume , Hiroshi Nishida
发明人： Tatsuya Oku , Masato Hashizume , Hiroshi Nishida
IPC分类号： G06F1/00
CPC分类号： G06F1/12
摘要： A communication apparatus having a clock interface unit supplying a clock signal for synchronization, includes a clock extracting section for extracting a clock component from a receive signal, a decoding section for generating a decoded signal by decoding in a predetermined encoding form the clock component extracted by the clock extracting section, a frame converting section for creating a receive frame by converting the decoded signal to a frame in a predetermined frame form, a determining section for determining whether the predetermined encoding form and the predetermined frame form are right or not on a basis of the receive frame, a setting section for performing setting regarding the clock signal on a basis of the encoding form and frame form determined to be right by the determining section, and a clock signal output section for outputting the clock signal generated on a basis of the setting by the setting section.
摘要翻译： 具有提供用于同步的时钟信号的时钟接口单元的通信装置包括：时钟提取部分，用于从接收信号中提取时钟分量;解码部分，用于通过以预定的编码形式解码解码信号，由时钟分量提取时钟分量， 时钟提取部分，用于通过将解码信号转换为预定帧形式的帧来创建接收帧的帧转换部分，用于基于所述确定部分确定预定编码形式和预定帧形式是否是正确的 一个设置部分，用于根据由确定部分确定为正确的编码形式和帧形式来执行关于时钟信号的设置;以及时钟信号输出部分，用于输出基于 由设置部分设置。
-
-
-
-
-
-
搜索结果
7 条记录 (耗时 0.023 秒)
