公开(公告)号：US5761141A

公开(公告)日：1998-06-02

申请号：US782038

申请日：1997-01-13

申请人： Hisao Kobashi ,  Yasuhiko Tsukikawa

发明人： Hisao Kobashi ,  Yasuhiko Tsukikawa

IPC分类号： G11C11/401 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/4094 ,  G11C29/00 ,  G11C29/24 ,  G11C29/34 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/34 ,  G11C11/4074 ,  G11C11/4094 ,  G11C29/24 ,  G11C5/147 ,  G11C29/50

摘要： A switching circuit for switching a bit line potential VBL of a DRAM to a power supply potential Vcc, an intermediate potential Vcc/2 or the ground potential GND is provided. In normal operation, the bit line potential VBL is set to Vcc/2. In a special write mode, Vcc or GND is applied to all the bit lines through an equalizer, a desired word line is raised to "H" level, and Vcc or GND is written to the storage nodes of all the memory cells connected to the word line. It is possible to write Vcc or GND even to the storage node of a memory cell which has been replaced by a redundant memory cell.

摘要翻译： 提供了用于将DRAM的位线电位VBL切换到电源电位Vcc，中间电位Vcc / 2或地电位GND的开关电路。 在正常操作中，位线电位VBL被设定为Vcc / 2。 在特殊写入模式下，Vcc或GND通过均衡器施加到所有位线，所需字线上升至“H”电平，Vcc或GND写入连接到所有位线的所有存储单元的存储节点 字线。 可以将Vcc或GND甚至写入由冗余存储单元替换的存储单元的存储节点。

公开(公告)号：US06392939B1

公开(公告)日：2002-05-21

申请号：US09615898

申请日：2000-07-13

申请人： Yoshiyuki Hikiyama ,  Hisao Kobashi ,  Tetsushi Hoshita

发明人： Yoshiyuki Hikiyama ,  Hisao Kobashi ,  Tetsushi Hoshita

IPC分类号： G11C700

CPC分类号： G11C29/50 ,  G11C29/34

摘要： During a burn-in test, a test mode signal TMRS is set to the H level, and word lines WL0 to WL3 can be activated by composite gates according to row address signals RA0 to RA3, respectively. Therefore, a potential difference and a high electric field are provided even between word lines WL0, WL2 during the burn-in test. Thus, the defect elimination rate during the burn-in test can be improved.

摘要翻译： 在老化测试期间，将测试模式信号TMRS设置为H电平，并且字线WL0至WL3可以分别根据行地址信号RA0至RA3由复合门激活。 因此，在老化试验期间，即使在字线WL0，WL2之间也提供电位差和高电场。 因此，可以提高老化试验中的缺陷消除率。

公开(公告)号：US6031782A

公开(公告)日：2000-02-29

申请号：US124514

申请日：1998-07-29

申请人： Hisao Kobashi ,  Mikio Sakurai ,  Susumu Tanida

发明人： Hisao Kobashi ,  Mikio Sakurai ,  Susumu Tanida

IPC分类号： G11C11/41 ,  G11C7/00 ,  G11C7/22 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/417 ,  H03F3/45

CPC分类号： G11C11/4076 ,  G11C11/406 ,  G11C7/22

摘要： A clock buffer in a semiconductor memory device includes two kinds of interface circuits, i.e., an LVTTL interface and an SSTL interface. When the semiconductor memory device is set to a specific mode (self-refresh mode) for suppressing a power consumption, the LVTTL is used for taking in an external signal. In a mode other than the self-refresh mode, the SSTL interface is used to take in an externally supplied signal. Thereby, a current can be suppressed in the specific mode.

摘要翻译： 半导体存储器件中的时钟缓冲器包括两种接口电路，即LVTTL接口和SSTL接口。 当半导体存储器件被设置为用于抑制功耗的特定模式（自刷新模式）时，LVTTL用于获取外部信号。 在自刷新模式以外的模式下，SSTL接口用于接收外部提供的信号。 由此，可以在特定模式中抑制电流。

公开(公告)号：US06335886B1

公开(公告)日：2002-01-01

申请号：US09725149

申请日：2000-11-29

申请人： Takehiro Ochi ,  Hisao Kobashi

发明人： Takehiro Ochi ,  Hisao Kobashi

IPC分类号： G11C700

CPC分类号： G11C29/70 ,  G11C11/4087 ,  G11C29/785 ,  G11C29/83

摘要： A redundancy row decoder in a DRAM includes a plurality of N channel MOS transistors connected in series between one terminal of each fuse and a line of a ground potential, the plurality of N channel MOS transistors having their gates receiving a predecode signal allocated to a corresponding word line. As compared with a conventional case where only one N channel MOS transistor is connected between one terminal of each fuse and the line of the ground potential, leakage current flowing through each fuse is made smaller.

摘要翻译： DRAM中的冗余行解码器包括串联连接在每个熔丝的一个端子和地电位之间的多个N沟道MOS晶体管，其多个N沟道MOS晶体管的栅极接收分配给相应的 字线。 与在每个熔丝的一个端子和地电位之间仅连接一个N沟道MOS晶体管的常规情况相比，流过每个熔丝的漏电流更小。