公开(公告)号：US20210158159A1

公开(公告)日：2021-05-27

申请号：US17092439

申请日：2020-11-09

Applicant: Hitachi, Ltd.

Inventor： Gou SHINKAI

IPC: G06N3/08 ,  H01L29/66 ,  G06N10/00

Abstract: To quickly find an optimal parameter for a neural network. An electronic circuit includes a quantum dot, a capacitance portion, a current portion, and a current adjustment portion. In this circuit, the quantum dot includes a first electrode, a second electrode, and a third electrode. The first electrode is connected to a first potential. The second electrode is connected to a first current source. The third electrode is connected to a second current source. The current portion discharges current from the second electrode or supplies current to the second electrode. The current adjustment portion adjusts a current of the current portion and outputs a parameter to adjust the current.

公开(公告)号：US20230297873A1

公开(公告)日：2023-09-21

申请号：US18073641

申请日：2022-12-02

Applicant: Hitachi, Ltd.

Inventor： Gou SHINKAI ,  Ryuta TSUCHIYA ,  Yusuke KANNO

IPC: G06N10/60

CPC classification number: G06N10/60

Abstract: Provided is a control method of a quantum bit including, when a two-quantum bit computation is performed on a plurality of pairs of quantum bits by a plurality of barrier transistors controlled collectively, selectively performing a one-quantum bit computation on a quantum bit selected from the plurality of pairs of quantum bits to selectively perform a two-quantum bit computation on a desired quantum bit pair selected from the plurality of pairs of quantum bits.

公开(公告)号：US20220271213A1

公开(公告)日：2022-08-25

申请号：US17590965

申请日：2022-02-02

Applicant: Hitachi, Ltd

Inventor： Digh HISAMOTO ,  Satoru AKIYAMA ,  Toshiyuki MINE ,  Noriyuki LEE ,  Gou SHINKAI ,  Shinichi SAITO ,  Ryuta TSUCHIYA

IPC: H01L39/22 ,  H01L27/18 ,  H01L39/24 ,  G06N10/40

Abstract: A semiconductor device includes an active region famed in a semiconductor layer formed on an insulating film famed in a semiconductor substrate and having a first extension portion extending in a first direction and a second extension portion extending in a second direction intersecting with the first direction, a first diffusion layer electrode of a first conductivity type provided in the first extension portion, second and third diffusion layer electrodes of a second conductivity type provided in the second extension portion so as to interpose a first connecting portion connecting the first extension portion and the second extension portion, a first gate electrode famed on the first extension portion between the first diffusion layer electrode and the first connecting portion through an insulating film famed on the semiconductor layer, and a second gate electrode famed on the first connecting portion through the insulating film famed on the semiconductor layer.