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    4h-SiC SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE
    2.
    发明申请
    4h-SiC SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE 有权
    4h-SiC半导体元件和半导体器件

    公开(公告)号：US20130146897A1

    公开(公告)日：2013-06-13

    申请号：US13684314

    申请日：2012-11-23

    Applicant: Hitachi, Ltd.

    Inventor： Hiroyuki YOSHIMOTO ,  Ryuta TSUCHIYA ,  Naoki TEGA ,  Digh HISAMOTO ,  Yasuhiro SHIMAMOTO ,  Yuki MORI

    IPC: H01L29/16

    CPC classification number: H01L29/1608 ,  H01L21/0475 ,  H01L21/049 ,  H01L29/045 ,  H01L29/41758 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7827

    Abstract: A trench groove is formed and a silicon oxide film is buried in the periphery of a channel region of (0001) surface 4h-SiC semiconductor element. The oxide film in the trench groove is defined in such a planar layout that a tensile strain is applied along the direction of the c-axis and a compressive strain is applied along two or more of axes on a plane perpendicular to the c-axis. For example, trench grooves buried with an oxide film may be configured to such a layout that they are in a trigonal shape surrounding the channel, or are arranged symmetrically with respect to the channel as a center when arranged discretely.

    Abstract translation: 形成沟槽，在（0001）面4h-SiC半导体元件的沟道区的周围埋置氧化硅膜。 沟槽中的氧化膜以这样的平面布局限定，使得沿着c轴的方向施加拉伸应变，并且沿着与c轴垂直的平面上的两个或更多个轴施加压缩应变。 例如，埋置有氧化物膜的沟槽沟可以被配置为使得它们处于围绕通道的三角形状，或者当离散布置时相对于通道对称地布置为中心。

    QUANTUM COMPUTER AND CONTROL METHOD THEREFOR
    3.
    发明公开
    QUANTUM COMPUTER AND CONTROL METHOD THEREFOR 审中-公开

    公开(公告)号：US20230409949A1

    公开(公告)日：2023-12-21

    申请号：US18115388

    申请日：2023-02-28

    Applicant: Hitachi, Ltd.

    Inventor： Takeru UTSUGI ,  Noriyuki LEE ,  Ryuta TSUCHIYA ,  Digh HISAMOTO ,  Toshiyuki MINE

    IPC: G06N10/40

    CPC classification number: G06N10/40

    Abstract: One preferred aspect of the invention is a quantum computer of a semiconductor, including: a semiconductor crystalline substrate; a gate electrode array structure formed on a surface of the semiconductor crystalline substrate; and a reservoir unit that is a carrier supply unit, in which a classic potential barrier is formed in the semiconductor crystalline substrate by controlling an applied voltage to the gate electrode array structure, and a charge supplied from the reservoir unit is transported into the classic potential barrier.

    SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    4.
    发明申请
    SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    硅碳化硅半导体器件及其制造方法

    公开(公告)号：US20150318389A1

    公开(公告)日：2015-11-05

    申请号：US14651555

    申请日：2012-12-28

    Applicant: HITACHI, LTD.

    Inventor： Ryuta TSUCHIYA ,  Hiroyuki MATSUSHIMA ,  Naoki TEGA ,  Digh HISAMOTO

    IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66

    CPC classification number: H01L29/7802 ,  H01L21/02529 ,  H01L21/0485 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/7813

    Abstract: When a gate length is reduced for the purpose of reducing on-resistance in a SiC DOMSFET, it is difficult to achieve both of the reduction of on-resistance by the reduction of gate length and the high element withstand voltage at the same time. In the present invention, a body layer is formed after the source diffusion layer region is formed and then a portion of the source diffusion layer region is recessed. Because of the presence of the body layer, the distances between the source diffusion region and respective end portions can be increased, a depletion layer is effectively expanded, and electric field concentration at the end portions can be suppressed, thereby improving withstand voltage characteristics. Consequently, the present invention can provide a silicon carbide semiconductor device that achieves both of the reduction of channel resistance by the reduction of gate length and the high element withstand voltage at the same time.

    Abstract translation: 为了降低SiC DOMSFET中的导通电阻而减小栅极长度，难以同时通过栅极长度的降低和高的元件耐受电压来实现导通电阻的降低。 在本发明中，在形成源极扩散层区域之后形成体层，然后使源极扩散层区域的一部分凹陷。 由于体层的存在，可以增大源极扩散区域和各个端部之间的距离，有效地扩大耗尽层，并且可以抑制端部的电场浓度，从而提高耐电压特性。 因此，本发明可以提供通过同时降低栅极长度和高元件耐受电压来实现沟道电阻降低的碳化硅半导体器件。

    CONTROL METHOD OF QUANTUM BIT AND QUANTUM COMPUTER
    5.
    发明公开
    CONTROL METHOD OF QUANTUM BIT AND QUANTUM COMPUTER 审中-公开

    公开(公告)号：US20230297873A1

    公开(公告)日：2023-09-21

    申请号：US18073641

    申请日：2022-12-02

    Applicant: Hitachi, Ltd.

    Inventor： Gou SHINKAI ,  Ryuta TSUCHIYA ,  Yusuke KANNO

    IPC: G06N10/60

    CPC classification number: G06N10/60

    Abstract: Provided is a control method of a quantum bit including, when a two-quantum bit computation is performed on a plurality of pairs of quantum bits by a plurality of barrier transistors controlled collectively, selectively performing a one-quantum bit computation on a quantum bit selected from the plurality of pairs of quantum bits to selectively perform a two-quantum bit computation on a desired quantum bit pair selected from the plurality of pairs of quantum bits.

    Semiconductor Device
    6.
    发明申请
    Semiconductor Device 有权

    公开(公告)号：US20220271213A1

    公开(公告)日：2022-08-25

    申请号：US17590965

    申请日：2022-02-02

    Applicant: Hitachi, Ltd

    Inventor： Digh HISAMOTO ,  Satoru AKIYAMA ,  Toshiyuki MINE ,  Noriyuki LEE ,  Gou SHINKAI ,  Shinichi SAITO ,  Ryuta TSUCHIYA

    IPC: H01L39/22 ,  H01L27/18 ,  H01L39/24 ,  G06N10/40

    Abstract: A semiconductor device includes an active region famed in a semiconductor layer formed on an insulating film famed in a semiconductor substrate and having a first extension portion extending in a first direction and a second extension portion extending in a second direction intersecting with the first direction, a first diffusion layer electrode of a first conductivity type provided in the first extension portion, second and third diffusion layer electrodes of a second conductivity type provided in the second extension portion so as to interpose a first connecting portion connecting the first extension portion and the second extension portion, a first gate electrode famed on the first extension portion between the first diffusion layer electrode and the first connecting portion through an insulating film famed on the semiconductor layer, and a second gate electrode famed on the first connecting portion through the insulating film famed on the semiconductor layer.

    QUANTUM INFORMATION PROCESSING SYSTEM AND QUANTUM INFORMATION PROCESSING METHOD OF QUANTUM INFORMATION PROCESSING SYSTEM
    8.
    发明公开
    QUANTUM INFORMATION PROCESSING SYSTEM AND QUANTUM INFORMATION PROCESSING METHOD OF QUANTUM INFORMATION PROCESSING SYSTEM 审中-公开

    公开(公告)号：US20240095566A1

    公开(公告)日：2024-03-21

    申请号：US18115092

    申请日：2023-02-28

    Applicant: Hitachi, Ltd.

    Inventor： Noriyuki LEE ,  Digh HISAMOTO ,  Ryuta TSUCHIYA

    IPC: G06N10/40 ,  G06N10/20

    CPC classification number: G06N10/40 ,  G06N10/20

    Abstract: A quantum bit array including a plurality of quantum dots capable of confining a quantum bit and a plurality of gate electrodes used to control of the plurality of quantum dots, and a control device controlling a plurality of quantum bits using the plurality of gate electrodes, the quantum bit array includes a storage region including a plurality of quantum dots storing the quantum bit, and an operation region including a plurality of quantum dots capable of applying a quantum gate operation of changing a spin state to the confined quantum bit, the stored quantum bit is moved from the storage region to the operation region by a shuttle operation of moving the quantum bit with a Coulomb force generated by using the plurality of gate electrodes, and the quantum gate operation of changing the spin state to the quantum bit is performed in the operation region.

    QUANTUM INFORMATION PROCESSING DEVICE
    9.
    发明申请
    QUANTUM INFORMATION PROCESSING DEVICE 有权

    公开(公告)号：US20220292383A1

    公开(公告)日：2022-09-15

    申请号：US17630266

    申请日：2020-03-12

    Applicant: Hitachi, Ltd.

    Inventor： Noriyuki LEE ,  Ryuta TSUCHIYA ,  Digh HISAMOTO

    IPC: G06N10/40

    Abstract: The first layer includes a first gate electrode array disposed in the first direction to control the qubits of the qubit string, and a second gate electrode array disposed in the first direction to control the inter-qubit interaction of the interaction string. The second layer includes a third gate electrode array disposed in the second direction, and a fourth gate electrode array disposed in the second direction adjacently to the third gate electrode array. The third and the fourth gate electrode arrays control a part of the multiple qubits, and a part of the multiple inter-qubit interactions, respectively.

    SEMICONDUCTOR DEVICE
    10.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130105812A1

    公开(公告)日：2013-05-02

    申请号：US13665194

    申请日：2012-10-31

    Applicant: Hitachi, Ltd.

    Inventor： Takashi ISHIGAKI ,  Ryuta TSUCHIYA ,  Kazuhiro MOCHIZUKI ,  Akihisa TERANO

    IPC: H01L29/78

    CPC classification number: H01L29/4236 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7787

    Abstract: A semiconductor device includes a nitride semiconductor stack having at least two hetero junction bodies where a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer are disposed, and includes a drain electrode and, a source electrode disposed to the nitride semiconductor stack, and gate electrodes at a position put between the drain electrode and the source electrode and disposed so as to oppose them respectively in which the drain electrode and the source electrode are disposed over the surface or on the lateral side of the nitride semiconductor stack, and the gate electrode has a first gate electrode disposed in the direction of the depth of the nitride semiconductor stack and a second gate electrode disposed in the direction of the depth of the nitride semiconductor at a depth different from the first gate electrode.

    Abstract translation: 半导体器件包括具有至少两个异质结体的氮化物半导体堆叠，其中设置具有比第一氮化物半导体层宽的带隙的第一氮化物半导体层和第二氮化物半导体层，并且包括漏电极， 设置在氮化物半导体堆叠上的源电极以及放置在漏电极和源电极之间的位置处的栅电极，并分别与漏电极和源电极配置在表面上或在其上 氮化物半导体堆叠的横向侧，并且栅电极具有沿氮化物半导体堆叠的深度方向设置的第一栅电极和沿氮化物半导体的深度方向设置的第二栅电极，其深度不同于 第一栅电极。

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