公开(公告)号：US20140159041A1

公开(公告)日：2014-06-12

申请号：US14095859

申请日：2013-12-03

Applicant: Hitachi, Ltd.

Inventor： Masanao YAMAOKA ,  Kenichi OSADA

IPC: H01L21/66

CPC classification number: H01L22/30 ,  H01L23/50 ,  H01L23/5286 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes: a first circuit block formed on a first semiconductor substrate having first and second sides extending in a first direction and third and fourth sides extending in a second direction intersecting with the first direction; a plurality of signal-line through vias that are connected to the first semiconductor substrate and transmit signals, which are output from the first circuit block, to a second circuit block formed on another second semiconductor substrate; and a plurality of power-supply through vias for supplying power to the first circuit block, and in the semiconductor device, the plurality of power-supply through vias are formed at edges of the first semiconductor substrate along the third and fourth sides and are formed in a plurality of rows in the first direction. Each circuit block has a power consuming mode in which power larger than the power consumption in a normal mode is consumed.

Abstract translation: 半导体器件包括：第一电路块，形成在第一半导体衬底上，第一和第二侧沿第一方向延伸，第三和第四侧沿与第一方向相交的第二方向延伸; 连接到第一半导体衬底并将从第一电路块输出的发射信号的多个信号线通孔传送到形成在另一第二半导体衬底上的第二电路块; 以及多个用于向第一电路块提供电力的通孔的供电通道，并且在半导体器件中，多个电源通孔沿着第三和第四侧形成在第一半导体衬底的边缘处，并且形成 在第一方向上的多行中。 每个电路块具有消耗大于正常模式的功耗的功率消耗模式。

公开(公告)号：US20160062704A1

公开(公告)日：2016-03-03

申请号：US14643567

申请日：2015-03-10

Applicant: Hitachi, Ltd.

Inventor： Masanao YAMAOKA ,  Kenichi OSADA ,  Chihiro YOSHIMURA

IPC: G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/0604 ,  G06F3/0638 ,  G06F11/3096 ,  G06F13/1668 ,  G06F17/18 ,  G06F17/3053 ,  G06F17/5009 ,  G06N7/005 ,  G06N99/002 ,  G11C11/1659

Abstract: In a semiconductor device in which components to be a basic configuration unit are arranged in an array shape for calculating an interaction model, a technique capable of changing a topology between the components is provided. A semiconductor device includes a plurality of units each of which includes a first memory cell for storing a value indicating a state of one node of an interaction model, a second memory cell for storing an interaction coefficient indicating an interaction from a node connected to the one node, and a calculation circuit for determining a value indicating a next state of the one node based on a value indicating a state of the connected node and on the interaction coefficient. In addition, the semiconductor device includes a plurality of switches for connecting or disconnecting the plurality of units to/from each other.

Abstract translation: 在作为基本配置单元的部件被布置为用于计算交互模型的阵列形状的半导体器件中，提供了能够改变部件之间的拓扑的技术。 半导体器件包括多个单元，每个单元包括用于存储指示交互模型的一个节点的状态的值的第一存储器单元，用于存储表示来自连接到一个节点的节点的交互的交互系数的第二存储器单元 节点，以及计算电路，用于基于指示所述连接节点的状态的值和所述交互系数来确定指示所述一个节点的下一状态的值。 此外，半导体器件包括用于将多个单元彼此连接或断开的多个开关。