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公开(公告)号：US20170262226A1
公开(公告)日：2017-09-14
申请号：US15504127
申请日：2014-09-03
Applicant: HITACHI, LTD.
Inventor： Masanao YAMAOKA , Chihiro YOSHIMURA
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673 , G06N7/005 , G06N99/002
Abstract: A semiconductor integrated circuit apparatus 23 is used for obtaining an optimum solution using an Ising model, and the semiconductor integrated circuit apparatus 23 includes plural spin cells 1 that are connected with each other. Here, each spin cell 1 includes: a memory cell 9(N) for memorizing a spin value; a computing circuit 10 for computing interactions among the plural spin cells that are connected with each other; a memory circuit 4 for holding at least one-bit data; and an inversion logic circuit LG capable of modifying a computed result obtained by the computing circuit in accordance with data held by the memory circuit 4. The computed result modified by a modification circuit in accordance with the data held by the memory circuit is memorized in the memory cell 9(N) included in each spin cell 1.
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公开(公告)号：US20170185380A1
公开(公告)日：2017-06-29
申请号：US15324178
申请日：2014-07-09
Applicant: HITACHI, LTD.
Inventor： Masato HAYASHI , Masanao YAMAOKA , Chihiro YOSHIMURA
CPC classification number: G06F7/588 , G06F17/18 , G06N7/005 , G06N99/002 , G11C11/16 , H01L27/11 , H03L7/26
Abstract: A spin unit provided with a memory cell that stores a value of one spin of an Ising model, a memory cell that stores an interaction coefficient from an adjacent spin which interacts with the corresponding spin, a memory cell that stores an external magnetic field coefficient of the one spin and circuits that determine the next state of the one spin on the basis of a product of a value of each adjacent spin and the corresponding interaction coefficient and the external magnetic field coefficient is configured, the semiconductor device is provided with a spin array where the plural spin units are arranged and connected on a two-dimensional plane on a semiconductor substrate, a random number generator and a bit regulator, the bit regulator operates output of the random number generator and supplies a random bit to all spin units in the spin array via one wire.
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公开(公告)号：US20160065210A1
公开(公告)日：2016-03-03
申请号：US14638205
申请日：2015-03-04
Applicant: HITACHI, LTD.
Inventor： Chihiro YOSHIMURA , Masanao YAMAOKA , Masato HAYASHI
IPC: H03K19/00
CPC classification number: H03K19/0002 , G06N7/005 , G06N99/005 , G11C11/1659 , G11C11/5607
Abstract: An object of the present invention is to realize an example of configuration that approximately represents a state of quantum spin in a semiconductor device where components as a basic configuration unit are arrayed so as to search a ground state of Ising model. There is disclosed a semiconductor device provided with plural units each of which is equipped with a first memory cell that stores a value which represents one spin of the Ising model by three or more states, a second memory cell that stores an interaction coefficient showing interaction from another spin which exerts interaction on the one spin and a logical circuit that determines the next state of the one spin on the basis of a function having a value which represents a state of the other spin and the interaction coefficient as a constant or a variable.
Abstract translation: 本发明的目的是实现一种近似表示半导体装置中的量子自旋状态的配置示例，其中将作为基本配置单元的组件排列以搜索Ising模型的基态。 公开了一种设置有多个单元的半导体器件，每个单元配备有第一存储器单元，其存储表示Ising模型的一个自旋的值由三个或更多个状态，第二存储单元，其存储显示相互作用的相互作用系数 基于具有表示另一个自旋的状态的值的函数和作为常数或变量的相互作用系数的函数确定一个自旋的下一个状态的逻辑电路的另一自旋在一个自旋上发生相互作用。
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公开(公告)号：US20240193454A1
公开(公告)日：2024-06-13
申请号：US18286836
申请日：2022-02-01
Applicant: Hitachi, Ltd.
Inventor： Yusuke KANNO , Hiroyuki MIZUNO , Chihiro YOSHIMURA
Abstract: A quantum computer system includes: a virtual quantum computer that simulates an operation of an actual quantum computer that executes a quantum operation using a quantum bit group based on a predetermined parameter; and a control device that controls the actual quantum computer and the virtual quantum computer, wherein the virtual quantum computer includes an estimation unit that estimates a state of a target quantum bit in the quantum bit group by simulating the operation of the actual quantum computer, and the control device includes a feedback control unit that changes the parameter and transmits the changed parameter to the virtual quantum computer until a deviation between an estimation state of the target quantum bit by the estimation unit and a quantum operation result from the actual quantum computer becomes a first design value or less.
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公开(公告)号：US20190155330A1
公开(公告)日：2019-05-23
申请号：US15754614
申请日：2015-08-24
Applicant: HITACHI, LTD.
Inventor： Masanao YAMAOKA , Takeshi KATO , Chihiro YOSHIMURA , Masato HAYASHI
Abstract: An aspect of the present invention for solving the above problem is a system including a first computer, a control module controlled by the first computer, and a second computer configured to be associated with the control module. The second computer includes a plurality of units, and each of the plurality of units includes a first memory that stores a value indicating a state of a node, a second memory that stores a coefficient, and an arithmetic circuit. The arithmetic circuit performs an arithmetic process of determining a value indicating a state of a node of its own unit, based on a value indicating a state of a node of a different unit and the coefficient of its own unit, and storing the determined value in the first memory. The control module supplies a control signal for controlling the arithmetic process to the second computer.
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Patent Agency Ranking
公开(公告)号：US20160064050A1
公开(公告)日：2016-03-03
申请号：US14642047
申请日：2015-03-09
Applicant: Hitachi, Ltd.
Inventor： Chihiro YOSHIMURA , Masanao YAMAOKA
CPC classification number: G11C7/12 , G06N7/005 , G06N99/002 , G11C5/02 , G11C5/147 , G11C8/08 , G11C8/10 , G11C11/412 , G11C11/419
Abstract: A semiconductor device includes a spin array in which a plurality of memory cells are disposed in a matrix configuration, a group of a predetermined number of memory cells is collected in units of spin units, and a plurality of the spin units are disposed with an adjacency; a word line provided in correspondence with rows of the memory cells; a bit line pair provided in correspondence with columns of the memory cells; a multiword decoder configured to multiplex a word address according to an input of a multiplicity specify signal to a word line and simultaneously activate a plurality of word lines; and a bit line driver configured to subject a plurality of memory cells, of the memory cells connected to bit line pairs and arrayed in a column direction, activated by the plurality of the word lines to a write operation or a read operation.
Abstract translation: 半导体器件包括其中多个存储单元以矩阵配置布置的自旋阵列，以自旋单元为单位收集预定数量的存储单元的组，并且多个自旋单元以邻接 ; 与存储单元的行对应地设置的字线; 与存储器单元的列相对应地提供的位线对; 多字解码器，被配置为根据多重指定信号的输入将字地址复用到字线并同时激活多个字线; 以及位线驱动器，其被配置为使由多个字线激活的存储单元连接到位线对并排列在列方向上的多个存储器单元进行写操作或读操作。
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公开(公告)号：US20160063725A1
公开(公告)日：2016-03-03
申请号：US14638613
申请日：2015-03-04
Applicant: Hitachi, Ltd.
Inventor： Chihiro YOSHIMURA
IPC: G06T7/00
CPC classification number: G06T7/0087 , G06N7/005 , G06N99/002 , G06T1/20 , G06T7/143 , G06T7/162 , G06T2207/20076 , G06T2207/20112
Abstract: A semiconductor device in which components each serving as a basic constitutional unit are arranged in order to find a solution of an interaction model. The semiconductor device includes multiple units each of which has: a first memory cell for scoring a value indicating a state of one node of the interaction model; a second memory cell for storing an interaction coefficient indicating an interaction from another node connected to the one node; a third memory cell for storing a flag for fixing a value of the first memory cell; a first arithmetic circuit that decides a next state of the one node based on a value indicating a state of the other node and the interaction coefficient; and a second arithmetic circuit that decides whether or not to record a value indicating the next state in the first memory cell according to a value of the flag.
Abstract translation: 为了找到交互模型的解决方案，布置有各自用作基本结构单元的部件的半导体器件。 半导体器件包括多个单元，每个单元具有：第一存储器单元，用于对表示交互模型的一个节点的状态进行评分; 第二存储器单元，用于存储指示来自连接到所述一个节点的另一节点的交互的交互系数; 第三存储器单元，用于存储用于固定第一存储单元的值的标志; 第一算术电路，其基于指示所述另一节点的状态的值和所述交互系数来决定所述一个节点的下一状态; 以及第二运算电路，其根据所述标志的值，决定是否在第一存储单元中记录表示下一状态的值。
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公开(公告)号：US20240070509A1
公开(公告)日：2024-02-29
申请号：US18112163
申请日：2023-02-21
Applicant: Hitachi, Ltd.
Inventor： Atsushi MIYAMOTO , Chihiro YOSHIMURA
Abstract: A control system for controlling a quantum computer is coupled to an analog control unit configured to generate a control signal for controlling a quantum bit device including a plurality of quantum bits. The control system converts, first control flow data which is described in a code format and defines control details of the quantum bit device into second control flow data which defines the control details of the quantum bit device by the analog control unit; and generate a plurality of the control data patterns from the second control flow data based on the third setting information.
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公开(公告)号：US20160064053A1
公开(公告)日：2016-03-03
申请号：US14639589
申请日：2015-03-05
Applicant: Hitachi Ltd.
Inventor： Masanao YAMAOKA , Chihiro YOSHIMURA
IPC: G11C7/22 , G11C14/00 , G11C11/411 , G06F12/02 , G11C11/406
CPC classification number: G11C7/222 , G06F12/0246 , G06F2212/7201 , G06N7/005 , G06N99/002 , G11C11/40615 , G11C11/411
Abstract: A semiconductor device has a plurality of units, each of which includes a first memory cell that stores a value indicating a state of one node of an interaction model, a second memory cell that stores an interaction coefficient indicating an interaction from a node connected to the one node, and a third memory cell that stores a bias coefficient of the one node. Furthermore, the semiconductor device has a computing circuit that determines a value indicating a next state of the one node based on a value indicating a state of the connected node, the interaction coefficient and the bias coefficient. Also, each of the second memory cell and the third memory cell in the plurality of units includes multi-valued memory cells.
Abstract translation: 半导体器件具有多个单元，每个单元包括存储指示交互模型的一个节点的状态的值的第一存储器单元，存储指示来自连接到所述交互模块的节点的交互的交互系数的第二存储器单元 一个节点和存储该一个节点的偏置系数的第三存储器单元。 此外，半导体器件具有基于表示连接节点的状态的值，相互作用系数和偏置系数来确定表示一个节点的下一状态的值的计算电路。 此外，多个单元中的第二存储单元和第三存储单元中的每一个包括多值存储单元。
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公开(公告)号：US20160063391A1
公开(公告)日：2016-03-03
申请号：US14645872
申请日：2015-03-12
Applicant: Hitachi, Ltd.
Inventor： Masato HAYASHI , Chihiro YOSHIMURA , Masanao YAMAOKA
CPC classification number: G06F7/588 , G06N7/005 , G06N99/00 , G06N99/002
Abstract: A highly-convenient information processing system capable of obtaining a solution of a problem under conditions desired by a user and a management apparatus capable of enhancing the convenience of the information processing system are suggested. An information processing system includes: a host unit equipped with one or more semiconductor chips that execute a ground-state search of an Ising model; and an operation unit that provides a user interface for a user to designate a problem; and a management unit that converts the problem designated by the user by using the user interface into the Ising model and controls the host unit to have the semiconductor chip perform the ground-state search of the converted Ising model; wherein the user can designate a condition for solving the problem by using the user interface; wherein the management unit generates an operating condition of the semiconductor chip according to the condition designated by the user and reports the generated operating condition and the Ising model of the problem designated by the user to the host unit; and wherein the host unit controls the semiconductor chip in accordance with the operating condition reported from the management unit.
Abstract translation: 提出一种能够在能够提高信息处理系统的便利性的用户和管理装置所期望的条件下获得问题的解决方案的高度方便的信息处理系统。 信息处理系统包括：配备有执行Ising模型的基态搜索的一个或多个半导体芯片的主机单元; 以及操作单元，其为用户提供用于指定问题的用户界面; 以及管理单元，其将用户指定的问题通过使用用户界面转换为Ising模型并且控制主机单元使半导体芯片执行对所转换的Ising模型的基态搜索; 其中所述用户可以通过使用所述用户界面来指定用于解决所述问题的条件; 其中，所述管理单元根据所述用户指定的条件生成所述半导体芯片的工作状态，并将所生成的操作条件和由所述用户指定的问题的所述Ising模型报告给所述主机单元; 并且其中所述主机单元根据从所述管理单元报告的操作条件来控制所述半导体芯片。
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