公开(公告)号：US20180246849A1

公开(公告)日：2018-08-30

申请号：US15758097

申请日：2015-11-25

申请人： HITACHI, LTD.

发明人： Takuya OKUYAMA ,  Masanao YAMAOKA

IPC分类号： G06F17/10 ,  H03K19/23 ,  G06F7/38

CPC分类号： G06F17/10 ,  G06F7/38 ,  H03K19/23

摘要： An object of the invention is to provide a majority circuit which may be manufactured cheaply and easily and may process necessary majority functions for calculation in an interaction model. The majority circuit according to the invention simplifies the processing of the majority function by using a bitonic sort circuit to round the sum of input signals to a power of 2.

公开(公告)号：US20180004860A1

公开(公告)日：2018-01-04

申请号：US15593428

申请日：2017-05-12

申请人： Hitachi, Ltd.

发明人： Junichi MIYAKOSHI ,  Masanao YAMAOKA ,  Hiromasa TAKAHASHI ,  Shirun HO ,  Kenzo KUROTSUCHI ,  Sanato NAGATA

IPC分类号： G06F17/30 ,  G06N99/00

摘要： A computer includes a data generation unit and a storage unit which retains graph information for managing a graph configured from a plurality of vertexes and sides. The data generation unit performs acquiring a plurality of data and graph information and assuring storage regions in number equal to the number of vertexes, converting each data into an input value and setting at least one input value to a storage region corresponding to at least one vertex, executing an updating process for updating a value set to a storage region corresponding to a first vertex using the value set to the storage region corresponding to the first vertex and a value set to a storage region corresponding to a different vertex directly connected to the first vertex, and outputting a set of values set to the storage regions corresponding to the vertexes as the feature value.

公开(公告)号：US20170270223A1

公开(公告)日：2017-09-21

申请号：US15505565

申请日：2014-08-22

申请人： HITACHI, LTD.

发明人： Takeshi KATO ,  Hiroyuki MIZUNO ,  Yasuyuki KUDO ,  Masanao YAMAOKA ,  Junichi MIYAKOSHI ,  Kouji FUKUDA ,  Yasuhiro ASA

IPC分类号： G06F17/30 ,  G06F7/14

CPC分类号： G06F16/904 ,  G06F7/14 ,  G06F16/9024 ,  G06F16/90335 ,  G06F16/9038 ,  G06N3/004

摘要： An object is to continuously provide new information which leads to awareness and discovery of a user.An autopoietic information processing system which is an information processing system for collecting and outputting information includes: a means that inputs first information; a means that collects second information related to the first information; a means that selects third information from the second information; a means that outputs second or third information; a means that collects the second information by setting the third information as new first information; a means that merges the existing second information and new second information at a predetermined rate; a means that selects new third information from the merged second information; and a means that outputs the merged second information or the new third information. The means are recursively operated.

公开(公告)号：US20160064053A1

公开(公告)日：2016-03-03

申请号：US14639589

申请日：2015-03-05

申请人： Hitachi Ltd.

发明人： Masanao YAMAOKA ,  Chihiro YOSHIMURA

IPC分类号： G11C7/22 ,  G11C14/00 ,  G11C11/411 ,  G06F12/02 ,  G11C11/406

CPC分类号： G11C7/222 ,  G06F12/0246 ,  G06F2212/7201 ,  G06N7/005 ,  G06N99/002 ,  G11C11/40615 ,  G11C11/411

摘要： A semiconductor device has a plurality of units, each of which includes a first memory cell that stores a value indicating a state of one node of an interaction model, a second memory cell that stores an interaction coefficient indicating an interaction from a node connected to the one node, and a third memory cell that stores a bias coefficient of the one node. Furthermore, the semiconductor device has a computing circuit that determines a value indicating a next state of the one node based on a value indicating a state of the connected node, the interaction coefficient and the bias coefficient. Also, each of the second memory cell and the third memory cell in the plurality of units includes multi-valued memory cells.

摘要翻译： 半导体器件具有多个单元，每个单元包括存储指示交互模型的一个节点的状态的值的第一存储器单元，存储指示来自连接到所述交互模块的节点的交互的交互系数的第二存储器单元 一个节点和存储该一个节点的偏置系数的第三存储器单元。 此外，半导体器件具有基于表示连接节点的状态的值，相互作用系数和偏置系数来确定表示一个节点的下一状态的值的计算电路。 此外，多个单元中的第二存储单元和第三存储单元中的每一个包括多值存储单元。

公开(公告)号：US20160063391A1

公开(公告)日：2016-03-03

申请号：US14645872

申请日：2015-03-12

申请人： Hitachi, Ltd.

发明人： Masato HAYASHI ,  Chihiro YOSHIMURA ,  Masanao YAMAOKA

IPC分类号： G06N7/00 ,  G06F7/58

CPC分类号： G06F7/588 ,  G06N7/005 ,  G06N99/00 ,  G06N99/002

摘要： A highly-convenient information processing system capable of obtaining a solution of a problem under conditions desired by a user and a management apparatus capable of enhancing the convenience of the information processing system are suggested. An information processing system includes: a host unit equipped with one or more semiconductor chips that execute a ground-state search of an Ising model; and an operation unit that provides a user interface for a user to designate a problem; and a management unit that converts the problem designated by the user by using the user interface into the Ising model and controls the host unit to have the semiconductor chip perform the ground-state search of the converted Ising model; wherein the user can designate a condition for solving the problem by using the user interface; wherein the management unit generates an operating condition of the semiconductor chip according to the condition designated by the user and reports the generated operating condition and the Ising model of the problem designated by the user to the host unit; and wherein the host unit controls the semiconductor chip in accordance with the operating condition reported from the management unit.

摘要翻译： 提出一种能够在能够提高信息处理系统的便利性的用户和管理装置所期望的条件下获得问题的解决方案的高度方便的信息处理系统。 信息处理系统包括：配备有执行Ising模型的基态搜索的一个或多个半导体芯片的主机单元; 以及操作单元，其为用户提供用于指定问题的用户界面; 以及管理单元，其将用户指定的问题通过使用用户界面转换为Ising模型并且控制主机单元使半导体芯片执行对所转换的Ising模型的基态搜索; 其中所述用户可以通过使用所述用户界面来指定用于解决所述问题的条件; 其中，所述管理单元根据所述用户指定的条件生成所述半导体芯片的工作状态，并将所生成的操作条件和由所述用户指定的问题的所述Ising模型报告给所述主机单元; 并且其中所述主机单元根据从所述管理单元报告的操作条件来控制所述半导体芯片。

公开(公告)号：US20160062704A1

公开(公告)日：2016-03-03

申请号：US14643567

申请日：2015-03-10

申请人： Hitachi, Ltd.

发明人： Masanao YAMAOKA ,  Kenichi OSADA ,  Chihiro YOSHIMURA

IPC分类号： G06F3/06

CPC分类号： G06F3/0673 ,  G06F3/0604 ,  G06F3/0638 ,  G06F11/3096 ,  G06F13/1668 ,  G06F17/18 ,  G06F17/3053 ,  G06F17/5009 ,  G06N7/005 ,  G06N99/002 ,  G11C11/1659

摘要： In a semiconductor device in which components to be a basic configuration unit are arranged in an array shape for calculating an interaction model, a technique capable of changing a topology between the components is provided. A semiconductor device includes a plurality of units each of which includes a first memory cell for storing a value indicating a state of one node of an interaction model, a second memory cell for storing an interaction coefficient indicating an interaction from a node connected to the one node, and a calculation circuit for determining a value indicating a next state of the one node based on a value indicating a state of the connected node and on the interaction coefficient. In addition, the semiconductor device includes a plurality of switches for connecting or disconnecting the plurality of units to/from each other.

摘要翻译： 在作为基本配置单元的部件被布置为用于计算交互模型的阵列形状的半导体器件中，提供了能够改变部件之间的拓扑的技术。 半导体器件包括多个单元，每个单元包括用于存储指示交互模型的一个节点的状态的值的第一存储器单元，用于存储表示来自连接到一个节点的节点的交互的交互系数的第二存储器单元 节点，以及计算电路，用于基于指示所述连接节点的状态的值和所述交互系数来确定指示所述一个节点的下一状态的值。 此外，半导体器件包括用于将多个单元彼此连接或断开的多个开关。

公开(公告)号：US20220343202A1

公开(公告)日：2022-10-27

申请号：US17635736

申请日：2019-10-29

申请人： Hitachi, Ltd.

发明人： Takuya OKUYAMA ,  Masanao YAMAOKA

IPC分类号： G06N10/60

摘要： An arithmetic circuit includes: a spin memory that stores a value indicating a state of one spin in an interaction model; an interaction coefficient auxiliary memory that stores an interaction coefficient of a subfunction corresponding to the spin memory; an external magnetic field coefficient auxiliary memory that stores an external magnetic field coefficient of the subfunction corresponding to the spin memory; a weight input line that receives a weight signal of the subfunction; an interaction coefficient calculation unit that calculates a weighted subfunction interaction coefficient by using the weight signal of the subfunction and the interaction coefficient of the subfunction; an external magnetic field coefficient calculation unit that calculates a weighted subfunction external magnetic field coefficient; and a next state calculation unit that calculates a next state of the spin based on the value of the spin, the weighted subfunction interaction coefficient, and the weighted subfunction external magnetic field coefficient.

公开(公告)号：US20180300287A1

公开(公告)日：2018-10-18

申请号：US15735033

申请日：2015-06-09

申请人： HITACHI, LTD.

发明人： Takuya OKUYAMA ,  Masanao YAMAOKA ,  Chihiro YOSHIMURA ,  Masato HAYASHI ,  Akihito AKAI

IPC分类号： G06F17/10

摘要： An information processing apparatus manufactured at low cost and with ease and that is capable of making a search for a ground state of an arbitrary Ising model. An information processing unit containing a plurality of semiconductor chips, each retains a value of one spin or values of a plurality of spins and simulates interactions among the spins, inter-chip wiring between the necessary semiconductor chips, and a control unit that cause each semiconductor chip to perform interaction computation. The control unit converts data of a problem into data of a lattice-shaped Ising model, which is possibly expressed by the plurality of semiconductor chips, without causing a spin arrangement, in a ground state of an Ising model for the problem, to be changed. The data of the lattice-shaped Ising model is divided for allocation to the plurality of semiconductor chips, and causes each semiconductor chip to perform the interaction computation.

公开(公告)号：US20170068632A1

公开(公告)日：2017-03-09

申请号：US15122553

申请日：2014-03-04

申请人： HITACHI, LTD.

发明人： Chihiro YOSHIMURA ,  Masanao YAMAOKA

IPC分类号： G06F13/40 ,  G06F1/32 ,  G06F17/50 ,  G06F13/28

CPC分类号： G06F13/4068 ,  G06F1/3296 ,  G06F13/28 ,  G06F17/5009 ,  G11C11/16

摘要： A semiconductor device in which a ground state of an Ising model is realized, includes a spin array in which a spin unit is formed, the spin unit including a memory cell storing a value of one spin in an Ising model, a memory cell storing an interaction coefficient from an adjacent spin interacting with the spin, a memory cell storing an external magnetic field coefficient of the spin, and a circuit deciding a next state of the spin by binary majority decision logic based on a product of the value of each of the adjacent spins and the corresponding interaction coefficient, and the external magnetic field coefficient. The spin array is formed by having a plurality of the spin units, each having each spin allocated thereto, arranged and connected on a two-dimensional plane on a semiconductor substrate in the state where a topology of the Ising model is maintained.

摘要翻译： 实现了伊辛模型的基态的半导体器件包括其中形成有自旋单元的自旋阵列，该自旋单元包括在伊辛模型中存储一个自旋值的存储单元，存储单元 与自旋相互作用的相互作用系数，存储有旋转的外部磁场系数的存储单元，以及通过二进制多数决定逻辑决定下一个旋转状态的电路，该电路基于每个 相邻的自旋和相应的相互作用系数，以及外部磁场系数。 自旋阵列通过在保持Ising模型的拓扑结构的状态下，通过在半导体衬底上设置并连接在二维平面上的多个旋转单元，每个旋转单元分别具有分配的每个自旋。

公开(公告)号：US20160118106A1

公开(公告)日：2016-04-28

申请号：US14890335

申请日：2013-05-31

申请人： HITACHI, LTD.

发明人： CHIHIRO YOSHIMURA ,  Masanao YAMAOKA ,  Tomonori SEKIGUCHI ,  Tatsuya TOMARU

IPC分类号： G11C11/419

CPC分类号： G11C11/419 ,  G06F7/588 ,  G06N3/08 ,  G11C7/04 ,  G11C7/1006 ,  G11C11/1675

摘要： It is an object of the present invention to provide a device which can be easily manufactured and obtain a ground state of an arbitrary Ising model. A semiconductor device includes a first memory cell and a second memory cell that interacts with the first memory cell, in which storage content of the first memory cell and the second memory cell is stochastically inverted. The storage content is stochastically inverted by dropping threshold voltages of the first memory cell and the second memory cell. The threshold voltages of the first and second memory cells are dropping by controlling substrate biases, power voltages, or trip points of the first and second memory cells.

摘要翻译： 本发明的一个目的是提供一种易于制造并获得任意伊辛模型的基态的装置。 半导体器件包括第一存储器单元和与第一存储器单元相互作用的第二存储器单元，其中第一存储单元和第二存储器单元的存储内容随机转换。 通过降低第一存储单元和第二存储单元的阈值电压，存储内容随机地反转。 通过控制第一和第二存储器单元的衬底偏置，电源电压或跳变点，第一和第二存储器单元的阈值电压下降。