公开(公告)号：US20240162297A1

公开(公告)日：2024-05-16

申请号：US18494035

申请日：2023-10-25

Applicant: Hitachi, Ltd.

Inventor： Takeru SUTO ,  Keisuke KOBAYASHI ,  Tomoka SUEMATSU ,  Haruka SHIMIZU

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/80

CPC classification number: H01L29/1608 ,  H01L29/0696 ,  H01L29/7832 ,  H01L29/806

Abstract: A silicon carbide semiconductor device includes: a trench formed on an upper surface of a silicon carbide semiconductor substrate; a gate electrode in the trench; an n-type drift layer, a p-type guard region, an n-type semiconductor region to which a source potential is applied, a p-type body layer and an n-type current diffusion region that have a lower impurity concentration than that of the guard region, the n-type drift layer, the p-type guard region, the n-type semiconductor region, the p-type body layer, and the n-type current diffusion region being formed in the silicon carbide semiconductor substrate; and an n-type JFET region that is formed in the silicon carbide semiconductor substrate so as to be separated from the trench and that connects the current diffusion region and the drift layer. The semiconductor region is separated from the drift layer, the current diffusion region, and the JFET region.

公开(公告)号：US20210143255A1

公开(公告)日：2021-05-13

申请号：US17080946

申请日：2020-10-27

Applicant: HITACHI, LTD.

Inventor： Takeru SUTO ,  Naoki TEGA ,  Naoki WATANABE ,  Hiroshi MIKI

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

Abstract: Provided is a semiconductor device whose performance is improved. A p type body region is formed in an n type semiconductor layer containing silicon carbide, and a gate electrode is formed on the body region with a gate insulating film interposed therebetween. An n type source region is formed in the body region on a side surface side of the gate electrode, and the body region and a source region are electrically connected to a source electrode. A p type field relaxation layer FRL is formed in the semiconductor layer on the side surface side of the gate electrode, and the source electrode is electrically connected to the field relaxation layer FRL. The field relaxation layer FRL constitutes a part of the JFET 2Q which is a rectifying element, and a depth of the field relaxation layer FRL is shallower than a depth of the body region.

公开(公告)号：US20190229211A1

公开(公告)日：2019-07-25

申请号：US16216333

申请日：2018-12-11

Applicant: HITACHI, LTD.

Inventor： Yuan BU ,  Hiroshi MIKI ,  Naoki TEGA ,  Naoki WATANABE ,  Digh HISAMOTO ,  Takeru SUTO

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/417 ,  H01L29/36 ,  H01L29/423 ,  H01L29/47 ,  H01L29/04 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/08 ,  H01L29/10

Abstract: A silicon carbide semiconductor device includes an n-type silicon carbide semiconductor substrate, a drain electrode electrically connected to a rear face, an n-type semiconductor layer having a second impurity concentration lower than the first impurity concentration, a p-type first semiconductor region, an n-type second semiconductor region, an n-type third semiconductor region, a trench having a first side face and a second side face opposing to each other and a third side face intersecting with the first side face and the second side face, a gate electrode formed in the trench with a gate insulating film interposed therebetween, a metal layer electrically connected to the third semiconductor region, and a source electrode electrically connecting the second semiconductor region and the metal layer to each other.