-
1.发明申请CIRCUIT AND METHOD FOR GENERATING INTERNAL VOLTAGE, AND SEMICONDUCTOR DEVICE HAVING THE CIRCUIT 有权用于产生内部电压的电路和方法，以及具有电路的半导体器件公开(公告)号：US20110095814A1
公开(公告)日：2011-04-28
申请号：US12845279
申请日：2010-07-28
Applicant: So-Young Kim , Jung Sik Kim , Jang-Woo Ryu , Ho Cheol Lee , Jung Bae Lee
Inventor： So-Young Kim , Jung Sik Kim , Jang-Woo Ryu , Ho Cheol Lee , Jung Bae Lee
IPC: G05F1/10
CPC classification number: G11C5/14
Abstract: An internal voltage generating method performed in a semiconductor device, the internal voltage generating method including generating a plurality of initialization signals corresponding to a plurality of external power supply voltages; detecting a transition of a lastly-generated initialization signal from among the plurality of initialization signals and generating a detection signal; and generating a first internal voltage according to the detection signal.
Abstract translation: 一种在半导体器件中执行的内部电压产生方法，所述内部电压产生方法包括产生对应于多个外部电源电压的多个初始化信号; 检测来自所述多个初始化信号中的最后生成的初始化信号的转变并产生检测信号; 以及根据检测信号产生第一内部电压。
-
公开(公告)号：US06337829B1
公开(公告)日：2002-01-08
申请号：US09648283
申请日：2000-08-24
Applicant: Ho Cheol Lee
Inventor： Ho Cheol Lee
IPC: G11C800
CPC classification number: G11C29/88 , G11C29/883
Abstract: A semiconductor memory device which includes a plurality of memory cell array blocks, each block including 2n partial blocks selectable in response to n address bits among a plurality of bits address. A partial block select signal generator is used for selecting ½n partial blocks of the 2n partial blocks in each of the plurality of memory cell array blocks by selecting the state of corresponding address bits among the n address bits. A method for repairing a semiconductor memory device which includes a plurality of memory cell array blocks and 2n partial blocks selected by the plurality of memory cell array blocks each responding to n address bits among a plurality of address bits, the method includes selecting only the ½n functional partial blocks of the 2n partial blocks in each of the plurality of memory cell array blocks by selecting the state of corresponding address bits among the n bits of address information.
Abstract translation: 一种半导体存储器件，包括多个存储单元阵列块，每个块包括响应于多个位地址中的n个地址位而可选择的2n个部分块。 通过选择n个地址位中相应的地址位的状态，使用部分块选择信号发生器来选择多个存储单元阵列块中的每一个中的2n个部分块的1/2个部分块。 一种修复半导体存储器件的方法，该半导体存储器件包括多个存储单元阵列块和由多个存储单元阵列块选择的2n个部分块，每个部分块响应多个地址位中的n个地址位，该方法包括仅选择½n 通过选择地址信息的n位中的相应地址位的状态，在多个存储单元阵列块的每一个中的2n个部分块的功能部分块。
-
公开(公告)号：US08476767B2
公开(公告)日：2013-07-02
申请号：US12762615
申请日：2010-04-19
Applicant: Ho Cheol Lee
Inventor： Ho Cheol Lee
IPC: H01L23/48
CPC classification number: G11C5/06 , G11C5/02 , H01L25/0657 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: A stacked layer type semiconductor device includes N memories each including at least one main via and (N−1) sub vias, the N memories being sequentially stacked on one-another so that central axes of the N memories face each other crosswise, and a plurality of connection units electrically connecting the N memories. Here, N is a natural number greater than 1.
Abstract translation: 堆叠层型半导体器件包括N个存储器，每个存储器包括至少一个主通孔和（N-1）个子通孔，N个存储器依次堆叠在一起，使得N个存储器的中心轴互相面对，并且 多个连接单元电连接N个存储器。 这里，N是大于1的自然数。
-
Patent Agency Ranking
4.发明申请Stacked Layer Type Semiconductor Device and Semiconductor System Including the Same 有权堆叠层类型半导体器件和包括其的半导体系统公开(公告)号：US20100314772A1
公开(公告)日：2010-12-16
申请号：US12762615
申请日：2010-04-19
Applicant: Ho Cheol Lee
Inventor： Ho Cheol Lee
IPC: H01L23/48
CPC classification number: G11C5/06 , G11C5/02 , H01L25/0657 , H01L2224/0554 , H01L2224/05573 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: A stacked layer type semiconductor device includes N memories each including at least one main via and (N−1) sub vias, the N memories being sequentially stacked on one-another so that central axes of the N memories face each other crosswise, and a plurality of connection units electrically connecting the N memories. Here, N is a natural number greater than 1.
Abstract translation: 堆叠层型半导体器件包括N个存储器，每个存储器包括至少一个主通孔和（N-1）个子通孔，N个存储器依次堆叠在一起，使得N个存储器的中心轴互相面对，并且 多个连接单元电连接N个存储器。 这里，N是大于1的自然数。
-
公开(公告)号：USD571763S1
公开(公告)日：2008-06-24
申请号：US29274697
申请日：2007-05-16
Applicant: Ho Cheol Lee
Designer： Ho Cheol Lee
-
6.发明授权Circuit and method for generating internal voltage, and semiconductor device having the circuit 有权用于产生内部电压的电路和方法，以及具有该电路的半导体器件公开(公告)号：US08278992B2
公开(公告)日：2012-10-02
申请号：US12845279
申请日：2010-07-28
Applicant: So-Young Kim , Jung Sik Kim , Jang-Woo Ryu , Ho Cheol Lee , Jung Bae Lee
Inventor： So-Young Kim , Jung Sik Kim , Jang-Woo Ryu , Ho Cheol Lee , Jung Bae Lee
IPC: G05F1/10
CPC classification number: G11C5/14
Abstract: An internal voltage generating method performed in a semiconductor device, the internal voltage generating method including generating a plurality of initialization signals corresponding to a plurality of external power supply voltages; detecting a transition of a lastly-generated initialization signal from among the plurality of initialization signals and generating a detection signal; and generating a first internal voltage according to the detection signal.
Abstract translation: 一种在半导体器件中执行的内部电压产生方法，所述内部电压产生方法包括产生对应于多个外部电源电压的多个初始化信号; 检测来自所述多个初始化信号中的最后生成的初始化信号的转变并产生检测信号; 以及根据检测信号产生第一内部电压。
-
公开(公告)号：USD645491S1
公开(公告)日：2011-09-20
申请号：US29365838
申请日：2010-07-15
Applicant: Ho Cheol Lee
Designer： Ho Cheol Lee
-
公开(公告)号：USD637576S1
公开(公告)日：2011-05-10
申请号：US29365857
申请日：2010-07-15
Applicant: Ho Cheol Lee
Designer： Ho Cheol Lee
-
-
-
-
-
-
-
Search Results
8
records
(took 0.013 seconds)
