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28 条记录 (耗时 0.022 秒)

    Optimized photodiode process for improved transfer gate leakage
    1.
    发明申请
    Optimized photodiode process for improved transfer gate leakage 有权
    优化光电二极管工艺，改善传输门漏电

    公开(公告)号：US20050167708A1

    公开(公告)日：2005-08-04

    申请号：US11094363

    申请日：2005-03-31

    申请人： Howard Rhodes ,  Richard Mauritzson ,  Inna Patrick

    发明人： Howard Rhodes ,  Richard Mauritzson ,  Inna Patrick

    IPC分类号： H01L21/00 ,  H01L27/146 ,  H01L31/0352 ,  H01L31/062 ,  H01L31/103

    CPC分类号： H01L27/14643 ,  H01L27/14601 ,  H01L31/03529 ,  H01L31/103 ,  Y02E10/50

    摘要： An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by a first, second and third implant, wherein at least one of the implants are angled so as to allow the resulting photodiode to extend out beneath an adjoining gate. Under an alternate embodiment, a fourth implant is added, under an increased implant angle, in the region of the second implant. The resulting photodiode structure substantially reduces or eliminates transfer gate subthreshold leakage.

    摘要翻译： 公开了一种图像感测电路和方法，其中通过一系列成角度的植入物在基板中形成光电二极管。 光电二极管由第一，第二和第三植入物形成，其中植入物中的至少一个是成角度的，以便使得到的光电二极管延伸出邻近的栅极之下。 在替代实施例中，在第二植入物的区域内以增加的植入角度添加第四植入物。 所得到的光电二极管结构基本上减少或消除传输门极阈值泄漏。

    Well for CMOS imager and method of formation
    3.
    发明申请
    Well for CMOS imager and method of formation 有权
    好的CMOS成像器和形成方法

    公开(公告)号：US20070080424A1

    公开(公告)日：2007-04-12

    申请号：US11636658

    申请日：2006-12-11

    申请人： Howard Rhodes ,  Inna Patrick ,  Richard Mauritzson

    发明人： Howard Rhodes ,  Inna Patrick ,  Richard Mauritzson

    IPC分类号： H01L29/00

    CPC分类号： H01L27/1463 ,  H01L27/14601 ,  H01L27/14689

    摘要： A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.

    摘要翻译： 公开了位于第一导电类型的衬底中并且低于晶体管栅极的电活性部分的沟道长度的约一半的第一导电类型的阱区。 阱区域从第二导电类型的钉扎光电二极管的电荷收集区域横向移位。

    N-well barrier pixels for improved protection of dark reference columns and rows from blooming and crosstalk
    7.
    发明申请
    N-well barrier pixels for improved protection of dark reference columns and rows from blooming and crosstalk 审中-公开
    N阱势垒像素，用于改善暗参考柱和行的防范和串扰的保护

    公开(公告)号：US20070246788A1

    公开(公告)日：2007-10-25

    申请号：US11408194

    申请日：2006-04-21

    申请人： Richard Mauritzson ,  Inna Patrick

    发明人： Richard Mauritzson ,  Inna Patrick

    IPC分类号： H01L27/14 ,  H01L21/00

    CPC分类号： H01L27/14654 ,  H01L27/1463 ,  H01L27/14689

    摘要： The barrier region for isolating one or more dark regions of the pixel array of an image sensor from the active array or from the peripheral circuitry includes N-well pixel isolation region. The N-well pixel isolation region includes at least one N-well implant or at least one N-well stripe. The N-well pixel isolation region is adjacent the pixel cells which comprise the dark region. The addition of the N-well in the barrier region improves the isolation properties of the barrier region by reducing or eliminating the neutral P− EPI region in the barrier pixel area below the N-well isolation region.

    摘要翻译： 用于将图像传感器的像素阵列的一个或多个暗区域与有源阵列或外围电路隔离的势垒区域包括N阱像素隔离区域。 N阱像素隔离区域包括至少一个N阱注入或至少一个N阱条纹。 N阱像素隔离区域与包括暗区域的像素单元相邻。 通过减少或消除N阱隔离区域之下的势垒像素区域中的中性P- EPI区域，在屏障区域中添加N-阱提高了屏障区域的隔离性能。

    Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation
    8.
    发明申请
    Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation 有权
    具有超浅结的光电二极管，用于高量子效率CMOS图像传感器和形成方法

    公开(公告)号：US20080096302A1

    公开(公告)日：2008-04-24

    申请号：US11783040

    申请日：2007-04-05

    申请人： Chandra Mouli ,  Howard Rhodes ,  Richard Mauritzson

    发明人： Chandra Mouli ,  Howard Rhodes ,  Richard Mauritzson

    IPC分类号： H01L31/00

    CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/0352 ,  H01L31/101

    摘要： A pinned photodiode with an ultra-shallow highly-doped surface layer of a first conductivity type and a method of formation are disclosed. The ultra-shallow highly-doped surface latter has a thickness of about 100 Angstroms to about 500 Angstroms and a dopant concentration of about 5×1017 atoms per cm3 to about 1×1019 atoms per cm3. The ultra-shallow highly-doped surface layer is formed by diffusion of ions from a doped layer into the substrate or by a plasma doping process. The ultra-shallow pinned layer is in contact with a charge collection region of a second conductivity type.

    摘要翻译： 公开了具有第一导电类型的超浅高掺杂表面层和形成方法的钉扎光电二极管。 超浅高掺杂表面层的厚度为约100埃至约500埃，掺杂剂浓度约5×10 17原子/ cm 3至约1×10 3原子/ SUP> 19个/ cm 3原子/ cm 3。 超浅高掺杂表面层通过将离子从掺杂层扩散到衬底中或通过等离子体掺杂工艺形成。 超浅钉扎层与第二导电类型的电荷收集区域接触。

    Contacts for CMOS imagers and method of formation
    10.
    发明申请
    Contacts for CMOS imagers and method of formation 有权

    公开(公告)号：US20060043436A1

    公开(公告)日：2006-03-02

    申请号：US11213935

    申请日：2005-08-30

    申请人： Xiaofeng Fan ,  Richard Mauritzson ,  Howard Rhodes

    发明人： Xiaofeng Fan ,  Richard Mauritzson ,  Howard Rhodes

    IPC分类号： H01L31/113 ,  H01L31/062

    CPC分类号： H01L27/14603 ,  H01L23/485 ,  H01L27/14636

    摘要： Low leakage contacts on leakage sensitive areas of a CMOS imager, such as a floating diffusion region or a photodiode, are disclosed. At least one low leakage polysilicon contact is provided over a leakage sensitive area of a CMOS imager. The polysilicon contact comprises a polysilicon region in direct contact with the area of interest (the leakage sensitive area) and a metal region located over the polysilicon region. The polysilicon contact provides an improved ohmic contact with less leakage into the substrate. The polysilicon contact may be provided with other conventional metal contacts, which are employed in areas of the CMOS imager that do not require low leakage.