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    Displaying device with predetermined pattern for repairing electrical defects and related methods
    2.
    发明申请
    Displaying device with predetermined pattern for repairing electrical defects and related methods 有权
    用于修复电气缺陷和相关方法的预定模式的显示装置

    公开(公告)号：US20050259190A1

    公开(公告)日：2005-11-24

    申请号：US11119342

    申请日：2005-04-28

    申请人： Chung-Yi Wang ,  Rung-Nan Lu

    发明人： Chung-Yi Wang ,  Rung-Nan Lu

    IPC分类号： G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

    CPC分类号： G02F1/136213 ,  G02F1/136259

    摘要： A displaying device at least comprises a thin film transistor (TFT); a first electrode controlled by the TFT; a first capacitor electrode and a second capacitor electrode electrically connected to each other through the first electrode. The first electrode has a first slit. The first slit is positioned between a first zone and a second zone, wherein the first zone connects the first capacitor electrode and the first electrode, and the second zone connects the second capacitor electrode and the first electrode. If a defect is observed, a portion of the first electrode is removed for isolating the first capacitor electrode and the second capacitor electrode.

    摘要翻译： 显示装置至少包括薄膜晶体管（TFT）; 由TFT控制的第一电极; 通过第一电极彼此电连接的第一电容器电极和第二电容器电极。 第一电极具有第一狭缝。 第一狭缝位于第一区域和第二区域之间，其中第一区域连接第一电容器电极和第一电极，第二区域连接第二电容器电极和第一电极。 如果观察到缺陷，则去除第一电极的一部分以隔离第一电容器电极和第二电容器电极。

    Displaying device with predetermined pattern for repairing electrical defects having slit region in TFT controlled electrode in which a first slit therein corresponds to a space separating first and second capacitor electrodes
    4.
    发明授权
    Displaying device with predetermined pattern for repairing electrical defects having slit region in TFT controlled electrode in which a first slit therein corresponds to a space separating first and second capacitor electrodes 有权
    具有预定图案的显示装置，用于修复TFT控制电极中具有狭缝区域的电气缺陷，其中第一狭缝中的第一狭缝对应于分隔第一和第二电容器电极的空间

    公开(公告)号：US07551254B2

    公开(公告)日：2009-06-23

    申请号：US11119342

    申请日：2005-04-28

    申请人： Chung-Yi Wang ,  Rung-Nan Lu

    发明人： Chung-Yi Wang ,  Rung-Nan Lu

    IPC分类号： G02F1/1337

    CPC分类号： G02F1/136213 ,  G02F1/136259

    摘要： A displaying device at least comprises a thin film transistor (TFT); a first electrode controlled by the TFT; a first capacitor electrode and a second capacitor electrode electrically connected to each other through the first electrode. The first electrode has a first slit. The first slit is positioned between a first zone and a second zone, wherein the first zone connects the first capacitor electrode and the first electrode, and the second zone connects the second capacitor electrode and the first electrode. If a defect is observed, a portion of the first electrode is removed for isolating the first capacitor electrode and the second capacitor electrode.

    摘要翻译： 显示装置至少包括薄膜晶体管（TFT）; 由TFT控制的第一电极; 通过第一电极彼此电连接的第一电容器电极和第二电容器电极。 第一电极具有第一狭缝。 第一狭缝位于第一区域和第二区域之间，其中第一区域连接第一电容器电极和第一电极，第二区域连接第二电容器电极和第一电极。 如果观察到缺陷，则去除第一电极的一部分以隔离第一电容器电极和第二电容器电极。

    VERTICALLY ALIGNED LCDS AND METHODS FOR DRIVING THE SAME
    5.
    发明申请
    VERTICALLY ALIGNED LCDS AND METHODS FOR DRIVING THE SAME 审中-公开
    垂直对准的液晶显示器及其驱动方法

    公开(公告)号：US20120169951A1

    公开(公告)日：2012-07-05

    申请号：US13243043

    申请日：2011-09-23

    申请人： Li-Wei Sung ,  Chung-Yi Wang ,  An-Chang Wang ,  Yao-Lien Hsieh

    发明人： Li-Wei Sung ,  Chung-Yi Wang ,  An-Chang Wang ,  Yao-Lien Hsieh

    IPC分类号： G02F1/133

    CPC分类号： G09G3/3655 ,  G02F1/1393 ,  G02F2001/133397 ,  G09G2300/0426 ,  G09G2320/0257

    摘要： The disclosed are methods for driving a vertically aligned (VA) LCD. The VALCD has an array substrate, an opposite substrate, and a liquid crystal layer disposed therebetween. The array substrate includes a common line, the opposite substrate includes a common electrode layer, and the liquid crystal layer has a threshold voltage. The common line is applied a higher positive voltage and the common electrode layer is applied a lower positive voltage, such that negative impurities are adsorbed on the common line. As such, image sticking problems are reduced.

    摘要翻译： 所公开的是用于驱动垂直对准（VA）LCD的方法。 VALCD具有阵列基板，相对基板和设置在其间的液晶层。 阵列基板包括公共线，相对的基板包括公共电极层，并且液晶层具有阈值电压。 公共线施加较高的正电压，并且公共电极层施加较低的正电压，使得负杂质吸附在公共线上。 因此，减少了图像粘附问题。

    Time-interleaved analog-to-digital converter having timing calibration
    6.
    发明授权
    Time-interleaved analog-to-digital converter having timing calibration 有权

    公开(公告)号：US07301486B2

    公开(公告)日：2007-11-27

    申请号：US11478679

    申请日：2006-07-03

    申请人： Chung-Yi Wang ,  Jieh-Tsorng Wu

    发明人： Chung-Yi Wang ,  Jieh-Tsorng Wu

    IPC分类号： H03M1/06

    CPC分类号： H03M1/1004 ,  H03M1/1215

    摘要： An analog-to-digital converter (ADC) having a two-channel or multi-channel structure processes background timing calibration. Signals from the ADC are directly compared for the calibration. Additional signal or interruption of circuit is not required. A dynamic calibration is processed. A timing-skew error is kept in a low level and a process mismatch is not a concern. Moreover, sampling frequency and input signal frequency are improved. A high sampling frequency and a high speed of signal inputting are achieved; and chip area can be greatly shrunk because the extra calibration circuits are simple digital circuits.

    Time-interleaved analog-to-digital converter having timing calibration
    7.
    发明申请
    Time-interleaved analog-to-digital converter having timing calibration 有权
    具有定时校准的时间交织的模数转换器

    公开(公告)号：US20070194960A1

    公开(公告)日：2007-08-23

    申请号：US11478679

    申请日：2006-07-03

    申请人： Chung-Yi Wang ,  Jieh-Tsorng Wu

    发明人： Chung-Yi Wang ,  Jieh-Tsorng Wu

    IPC分类号： H03M1/10

    CPC分类号： H03M1/1004 ,  H03M1/1215

    摘要： An analog-to-digital converter (ADC) having a two-channel or multi-channel structure processes background timing calibration. Signals from the ADC are directly compared for the calibration. Additional signal or interruption of circuit is not required. A dynamic calibration is processed. A timing-skew error is kept in a low level and a process mismatch is not a concern. Moreover, sampling frequency and input signal frequency are improved. A high sampling frequency and a high speed of signal inputting are achieved; and chip area can be greatly shrunk because the extra calibration circuits are simple digital circuits.

    摘要翻译： 具有双通道或多通道结构的模数转换器（ADC）处理后台定时校准。 直接比较来自ADC的信号进行校准。 不需要附加信号或电路中断。 处理动态校准。 定时偏移误差保持在低水平，并且过程不匹配不是问题。 此外，提取采样频率和输入信号频率。 实现了高采样频率和高速信号输入; 由于额外的校准电路是简单的数字电路，芯片面积可以大大缩小。