公开(公告)号：US06459751B1

公开(公告)日：2002-10-01

申请号：US09847978

申请日：2001-05-02

申请人： Hsing-Yi Chen ,  Jo-Yu Wang ,  Jyh-Ming Wang ,  Hsin-Kuang Chen ,  Min-Shun Liao

发明人： Hsing-Yi Chen ,  Jo-Yu Wang ,  Jyh-Ming Wang ,  Hsin-Kuang Chen ,  Min-Shun Liao

IPC分类号： G06M300

CPC分类号： G11C19/00 ,  G11C8/04 ,  G11C19/28

摘要： A multi-shifting shift register is adapted for outputting a selected address signal to a memory unit, and includes a control circuit for outputting a number (i) of shift signals and a timing pulse signal. One of the shift signals is at an enabled state and the other ones of the shift signals are at a disabled state during each cycle of the timing pulse signal. A multi-shifting circuit includes a number (N), which is larger than the number (i), of cascaded register units, each of which has a flip-flop that has an input end, and an output end for generating an address signal, and a selector that has the number (i) of select inputs for receiving the number (i) of the shift signals respectively from the control circuit, the number (i) of address signal inputs, and an output. The output end of the flip-flop is connected to a first one of the address signal inputs of the selector. The input end of the flip-flop of each of the register units is connected to the output of the selector of a preceding one of the register units. A jth one of the address signal inputs of the selector of each of the registers units is connected to the output end of the flip-flop of a (j−1)th preceding one of the register units. The number (j) is a number between 2 and i. The selected address signal is the address signal that is outputted by the flip-flop of one of the register units and that is at the enabled state.

摘要翻译： 多移位移位寄存器适于将选择的地址信号输出到存储单元，并且包括用于输出移位信号的数目（i）和定时脉冲信号的控制电路。 一个移位信号处于使能状态，另外一个位移信号在定时脉冲信号的每个周期期间处于禁用状态。 多移动电路包括大于数量（i）的数量（N）的级联寄存器单元，每个都具有具有输入端的触发器，以及用于产生地址信号的输出端 以及选择器，其具有分别从控制电路接收移位信号的数量（i）的选择输入的数量（i），地址信号输入的数量（i）和输出。 触发器的输出端连接到选择器的第一个地址信号输入端。 每个寄存器单元的触发器的输入端连接到前一个寄存器单元的选择器的输出端。 每个寄存器单元的选择器的地址信号输入中的第j个连接到第（j-1）个前一个寄存器单元的触发器的输出端。 数字（j）是2和i之间的数字。 选择的地址信号是由寄存器单元之一的触发器输出的处于使能状态的地址信号。

公开(公告)号：US06256262B1

公开(公告)日：2001-07-03

申请号：US09633967

申请日：2000-08-08

申请人： Hsing-Yi Chen ,  Jo-Yu Wang ,  Hsin-Kuang Chen ,  Jyh-Ming Wang

发明人： Hsing-Yi Chen ,  Jo-Yu Wang ,  Hsin-Kuang Chen ,  Jyh-Ming Wang

IPC分类号： G11C800

CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C7/22

摘要： A memory device includes a global decoder circuit and two memory cell array devices, each of which is disposed adjacent to a respective one of opposing first and second sides of the global decoder circuit, and has global word lines coupled to the global decoder circuit. Each of two data input buffers is disposed at a third side of the global decoder circuit adjacent to a respective one of the memory cell arrays, and is coupled to the respective one of the memory cell arrays. A write control circuit is coupled to and is disposed adjacent to the third side of the global decoder circuit. A write clock buffer is disposed adjacent to the third side of the global decoder circuit, and is coupled to the data input buffers. A read control circuit is coupled to and is disposed adjacent to a fourth side of the global decoder circuit. Each of two multiplexer sets is coupled to bit lines of a respective one of the memory cell array devices. Each of two output circuits is coupled to a respective one of the multiplexer sets. A read clock buffer is disposed adjacent to the fourth side of the global decoder circuit, and is coupled to the output circuits.

摘要翻译： 存储器件包括全局解码器电路和两个存储单元阵列器件，每个存储器单元阵列器件与全球解码器电路的相对的第一和第二侧的相应一个相邻地布置，并且具有耦合到全局解码器电路的全局字线。 两个数据输入缓冲器中的每一个被布置在与存储单元阵列的相应一个相邻的全局解码器电路的第三侧，并且耦合到存储单元阵列中的相应的一个。 一个写入控制电路耦合到全局解码器电路的第三侧并邻近其设置。 写时钟缓冲器被布置为与全局解码器电路的第三侧相邻，并且耦合到数据输入缓冲器。 读控制电路耦合到全局解码器电路的第四侧并与之配置。 两个多路复用器组中的每一个耦合到存储单元阵列器件的相应一个的位线。 两个输出电路中的每一个耦合到多路复用器集合中的相应一个。 读时钟缓冲器被布置为与全局解码器电路的第四侧相邻，并且耦合到输出电路。

公开(公告)号：US5943566A

公开(公告)日：1999-08-24

申请号：US84766

申请日：1998-05-26

申请人： Jyh-Ming Wang

发明人： Jyh-Ming Wang

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/8234

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S148/163

摘要： After the formation of a gate oxide layer, a polysilicon layer is formed right away. The polysilicon layer is used for patterning the gate oxide layer. The photolithography and etching processes of forming the buried contact window are combined with the step of removing the gate oxide layer at the periphery circuit region. Then, after the formation of the gate oxide layer at the memory cell region, one thermal oxidation process is performed to form the gate oxide layer at the periphery circuit region.

摘要翻译： 在形成栅极氧化物层之后，立即形成多晶硅层。 多晶硅层用于图案化栅极氧化物层。 形成埋入窗口的光刻和蚀刻工艺与在外围电路区域去除栅极氧化物层的步骤相结合。 然后，在存储单元区域形成栅极氧化层之后，进行一个热氧化处理，以在外围电路区域形成栅氧化层。

公开(公告)号：US6159840A

公开(公告)日：2000-12-12

申请号：US439930

申请日：1999-11-12

申请人： Jyh-Ming Wang

发明人： Jyh-Ming Wang

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/7682

摘要： A fabrication method for a dual damascene structure comprising an air-gap is provided. The method includes forming sequentially a first dielectric layer, a stop layer and a second dielectric layer on a substrate comprising a first metal layer. The first and the second dielectric layers are then defined to form a via. opening exposing the first metal layer and an opening in a predetermined position on the first and second dielectric layers. An oxide layer is then formed on the second dielectric layer covering the opening and forming a gap. The oxide layer and the second dielectric layer are then defined to form a trench, which exposes the first metal layer. A second metal layer and a via plug are then formed in the trench and the via. opening, wherein the second metal layer and the first metal layer are electrically connected through the via plug.

摘要翻译： 提供了一种包括气隙的双镶嵌结构的制造方法。 该方法包括在包括第一金属层的基板上依次形成第一介电层，停止层和第二介质层。 然后限定第一和第二介电层以形成通孔。 打开第一金属层和在第一和第二介电层上的预定位置的开口。 然后在覆盖开口的第二介电层上形成氧化层并形成间隙。 然后限定氧化物层和第二介电层以形成暴露第一金属层的沟槽。 然后在沟槽和通孔中形成第二金属层和通孔塞。 开口，其中所述第二金属层和所述第一金属层通过所述通孔插塞电连接。