公开(公告)号：US07499314B2

公开(公告)日：2009-03-03

申请号：US12002161

申请日：2007-12-14

申请人： Hsu Kai Yang ,  Po-Kang Wang ,  Xizeng Shi

发明人： Hsu Kai Yang ,  Po-Kang Wang ,  Xizeng Shi

IPC分类号： G11C11/00

CPC分类号： G11C7/14 ,  G11C11/16

摘要： An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines of pairs of the columns together at a location proximally to the sense amplifiers. The MRAM cells of a first of the pair of columns are programmed to a first magneto-resistive state and the MRAM cells of a second of the pair of columns are programmed to a second magneto-resistive state. When one row of data MRAM cells is selected for reading, a row of paired MRAM reference cells are placed in parallel to generate the mid-point reference current for sensing. The MRAM reference sub-array may be programmed electrically or aided by a magnetic field. A method for verifying programming of the MRAM reference sub-array is discussed.

摘要翻译： MRAM参考单元子阵列提供了一个中点参考电流来检测放大器。 MRAM参考单元子阵列具有以行和列排列的MRAM单元。 位线与子阵列的每一列相关联。 耦合将位列对的位线连接到读出放大器的近端位置。 一对列中的第一列的MRAM单元被编程为第一磁阻状态，并且该对列中的第二对的MRAM单元被编程为第二磁阻状态。 当选择一行数据MRAM单元进行读取时，并行放置一对配对的MRAM参考单元，以生成用于检测的中点参考电流。 MRAM参考子阵列可以被电场编程或由磁场辅助。 讨论了一种用于验证MRAM参考子阵列的编程的方法。

公开(公告)号：US20080266943A1

公开(公告)日：2008-10-30

申请号：US11789324

申请日：2007-04-24

申请人： Hsu Kai Yang ,  Po-Kang Wang

发明人： Hsu Kai Yang ,  Po-Kang Wang

IPC分类号： G11C11/14

CPC分类号： G11C11/16

摘要： A spin-torque MRAM array has MRAM cells arranged in rows and columns. Bit lines are connected to each of the MRAM cells on each column. Source select lines are connected to each MRAM cell of a pair of rows and are oriented orthogonally to the bit lines. Write lines are connected to the gate of the gating MOS transistor of each MRAM cell of the rows. The MRAM cells are written in a two step process with selected MRAM cells written to a first logic level (0) in a first step and selected MRAM cells written to a second logic level (1) in a second step. A second embodiment of the spin-torque MRAM array has the bit lines commonly connected together to receive the data and the source select lines commonly connected together to receive an inverse of the data for writing.

摘要翻译： 自旋扭矩MRAM阵列具有以行和列排列的MRAM单元。 位线连接到每列上的每个MRAM单元。 源选择线连接到一对行的每个MRAM单元并且与位线正交地定向。 写入线连接到行的每个MRAM单元的选通MOS晶体管的栅极。 MRAM单元以两步过程写入，在第一步骤中将所选MRAM单元写入第一逻辑电平（0），并在第二步骤中将所选择的MRAM单元写入第二逻辑电平（1）。 自旋扭矩MRAM阵列的第二实施例具有通常连接在一起的位线，以接收通常连接在一起的数据和源选择线，以接收用于写入的数据的倒数。

公开(公告)号：US07321507B2

公开(公告)日：2008-01-22

申请号：US11284299

申请日：2005-11-21

申请人： Hsu Kai Yang ,  Po-Kang Wang ,  Xizeng Shi

发明人： Hsu Kai Yang ,  Po-Kang Wang ,  Xizeng Shi

IPC分类号： G11C7/00

CPC分类号： G11C7/14 ,  G11C11/16

摘要： An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines of pairs of the columns together at a location proximally to the sense amplifiers. The MRAM cells of a first of the pair of columns are programmed to a first magneto-resistive state and the MRAM cells of a second of the pair of columns are programmed to a second magneto-resistive state. When one row of data MRAM cells is selected for reading, a row of paired MRAM reference cells are placed in parallel to generate the mid-point reference current for sensing. The MRAM reference sub-array may be programmed electrically or aided by a magnetic field. A method for verifying programming of the MRAM reference sub-array is discussed.

公开(公告)号：US07852662B2

公开(公告)日：2010-12-14

申请号：US11789324

申请日：2007-04-24

申请人： Hsu Kai Yang ,  Po-Kang Wang

发明人： Hsu Kai Yang ,  Po-Kang Wang

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： A spin-torque MRAM array has MRAM cells arranged in rows and columns. Bit lines are connected to each of the MRAM cells on each column. Source select lines are connected to each MRAM cell of a pair of rows and are oriented orthogonally to the bit lines. Write lines are connected to the gate of the gating MOS transistor of each MRAM cell of the rows. The MRAM cells are written in a two step process with selected MRAM cells written to a first logic level (0) in a first step and selected MRAM cells written to a second logic level (1) in a second step. A second embodiment of the spin-torque MRAM array has the bit lines commonly connected together to receive the data and the source select lines commonly connected together to receive an inverse of the data for writing.

摘要翻译： 自旋扭矩MRAM阵列具有以行和列排列的MRAM单元。 位线连接到每列上的每个MRAM单元。 源选择线连接到一对行的每个MRAM单元并且与位线正交地定向。 写入线连接到行的每个MRAM单元的选通MOS晶体管的栅极。 MRAM单元以两步过程写入，在第一步骤中将所选MRAM单元写入第一逻辑电平（0），并在第二步骤中将所选择的MRAM单元写入第二逻辑电平（1）。 自旋扭矩MRAM阵列的第二实施例具有通常连接在一起的位线，以接收通常连接在一起的数据和源选择线，以接收用于写入的数据的倒数。

公开(公告)号：US20100191896A1

公开(公告)日：2010-07-29

申请号：US12321663

申请日：2009-01-23

申请人： Hsu Kai Yang ,  Po-Kang Wang ,  Takuma Murai ,  Takehiro Kamigama

发明人： Hsu Kai Yang ,  Po-Kang Wang ,  Takuma Murai ,  Takehiro Kamigama

IPC分类号： G06F12/02 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0246 ,  G06F12/0873 ,  G06F2212/214 ,  G06F2212/7201 ,  G06F2212/7203

摘要： Systems and methods for a SSD controller enabling data transfer between a host and flash memories have been achieved. A major component of the SSD controller is a non-volatile buffer memory, which interfaces fast disk drive protocols and slow write and read cycles of NAND flash. Preferably MRAM or Phase Change RAM can be used for the buffer memory. Non-volatile tables can also be implemented for storing dynamic logical to physical address translation, defective sector information and their spare sectors and/or SSD configuration parameters. data are kept in a buffer memory when the buffer memory is not powered

摘要翻译： SSD控制器的系统和方法实现了主机和闪速存储器之间的数据传输。 SSD控制器的一个主要组成部分是非易失性缓冲存储器，它接口快速磁盘驱动器协议和NAND闪存的缓慢写入和读取周期。 优选地，MRAM或相变RAM可用于缓冲存储器。 还可以实现非易失性表，用于存储动态逻辑到物理地址转换，缺陷扇区信息及其备用扇区和/或SSD配置参数。 当缓冲存储器未通电时，数据保存在缓冲存储器中

公开(公告)号：US07480172B2

公开(公告)日：2009-01-20

申请号：US11339189

申请日：2006-01-25

申请人： Xizeng Shi ,  Po-Kang Wang ,  Hsu Kai Yang

发明人： Xizeng Shi ,  Po-Kang Wang ,  Hsu Kai Yang

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： An MRAM array has a plurality of MRAM devices that are arranged in rows and columns with segmented word lines. A magnetic biasing field is coupled to each of the MRAM devices. The MRAM devices are programmed by providing a bidirectional bit line current to a selected bit line of the plurality of bit lines and a word line current pulse to one word line segment of one row of word line segments by discharging coupled word line segments. The field biasing device may be permanent magnetic layers or write biasing lines in proximity to the fixed magnetic layer of each of the MRAM and has a magnetic orientation equivalent to the magnetic orientation of a word line segment magnetic field generated by the word line current pulse.

摘要翻译： MRAM阵列具有多个以分段字线排列成行和列的MRAM器件。 磁偏置场耦合到每个MRAM器件。 MRAM器件通过向多个位线的选定位线提供双向位线电流，并通过对耦合的字线段进行放电而将字线电流脉冲提供给一行字线段的一个字线段。 励磁偏置装置可以是永久磁性层或者写入偏置线，靠近每个MRAM的固定磁性层，并且具有与由字线电流脉冲产生的字线段磁场的磁性取向相当的磁性取向。

公开(公告)号：US07224628B2

公开(公告)日：2007-05-29

申请号：US11486192

申请日：2006-07-13

申请人： Hsu Kai Yang ,  Xi Zeng Shi ,  Po-Kang Wang ,  Bruce Yang

发明人： Hsu Kai Yang ,  Xi Zeng Shi ,  Po-Kang Wang ,  Bruce Yang

IPC分类号： G11C7/00

CPC分类号： G11C14/0081 ,  G11C11/1659 ,  G11C11/1675 ,  G11C29/02 ,  G11C29/08 ,  G11C29/50

摘要： Magnetic Random Access Memory (MRAM) can be programmed and read as fast as Static Random Access Memory (SRAM) and has the non-volatile characteristics of electrically eraseable programmable read only memory (EEPROM), FLASH EEPROM or one-time-programmable (OTP) EPROM. Due to the randomness of manufacturing process, the magnetic tunnel junctions (MTJ) in MRAM cells will require different row and column current combinations to program and not to disturb the other cells. Based on adaptive current sources for programming, this disclosure teaches methods, designs, test algorithms and manufacturing flows for generating EEPROM, FLASH EEPROM or OTP EPROM like memories from MRAM.

摘要翻译： 磁性随机存取存储器（MRAM）可以与静态随机存取存储器（SRAM）一样快速编程和读取，并且具有电可擦除可编程只读存储器（EEPROM），闪存EEPROM或一次可编程（OTP）的非易失性特性 ）EPROM。 由于制造过程的随机性，MRAM单元中的磁隧道结（MTJ）将需要不同的行和列电流组合来编程，而不会干扰其他单元。 基于用于编程的自适应电流源，本公开教导了用于从MRAM生成EEPROM，FLASH EEPROM或OTP EPROM的存储器的方法，设计，测试算法和制造流程。

公开(公告)号：US07180769B2

公开(公告)日：2007-02-20

申请号：US11103977

申请日：2005-04-12

申请人： Po-Kang Wang ,  Yin Rong ,  Hsu Kai Yang ,  Xizeng Shi

发明人： Po-Kang Wang ,  Yin Rong ,  Hsu Kai Yang ,  Xizeng Shi

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C11/15

摘要： The word line segment select transistor of a segmented word line array is placed on the word line current source side. This eliminates many undesirable effects currently associated with segmented word line MRAM arrays.

摘要翻译： 分段字线阵列的字线选择晶体管被放置在字线电流源侧。 这消除了目前与分段字线MRAM阵列相关联的许多不期望的影响。

公开(公告)号：US07609543B2

公开(公告)日：2009-10-27

申请号：US11904434

申请日：2007-09-27

申请人： Hsu Kai Yang ,  Lejan Pu ,  Perng-Fei Yuh ,  Po-Kang Wang

发明人： Hsu Kai Yang ,  Lejan Pu ,  Perng-Fei Yuh ,  Po-Kang Wang

IPC分类号： G11C11/00

CPC分类号： G11C11/16 ,  G11C29/06 ,  G11C29/08 ,  G11C29/12005

摘要： Voltage and current stress for magnetic random access memory (MRAM) cells can weed out potential early failure cells. Method and circuit implementation of such a stress test for a MRAM comprise coupling a stress test circuit to the read bus of the MRAM and stressing the Magnetic Tunnel Junctions (MTJS) by tying them to ground by activating isolation transistors associated with them. Read word lines control which MTJs are stressed Both the method and implementation can be used for any memory cells based on resistance differences, such as Phase RAM or Spin Valve MRAM.

摘要翻译： 磁性随机存取存储器（MRAM）电池的电压和电流应力可以消除潜在的早期故障电池。 用于MRAM的这种应力测试的方法和电路实现包括将应力测试电路耦合到MRAM的读总线，并通过激活与它们相关联的隔离晶体管将它们绑定到地来强调磁隧道接合点（MTJS）。 读取字线控制哪些MTJ受到压力这两种方法和实现都可以用于基于电阻差异的任何存储单元，如相位RAM或自旋阀MRAM。

公开(公告)号：US20090086531A1

公开(公告)日：2009-04-02

申请号：US11904434

申请日：2007-09-27

申请人： Hsu Kai Yang ,  Lejan Pu ,  Perng-Fei Yuh ,  Po-Kang Wang

发明人： Hsu Kai Yang ,  Lejan Pu ,  Perng-Fei Yuh ,  Po-Kang Wang

IPC分类号： G11C11/00 ,  G11C29/00

CPC分类号： G11C11/16 ,  G11C29/06 ,  G11C29/08 ,  G11C29/12005

摘要： Voltage and current stress for magnetic random access memory (MRAM) cells can weed out potential early failure cells. Method and circuit implementation of such a stress test for a MRAM comprise coupling a stress test circuit to the read bus of the MRAM and stressing the Magnetic Tunnel Junctions (MTJS) by tying them to ground by activating isolation transistors associated with them. Read word lines control which MTJs are stressed Both the method and implementation can be used for any memory cells based on resistance differences, such as Phase RAM or Spin Valve MRAM.