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    Method and implementation of stress test for MRAM
    1.
    发明授权
    Method and implementation of stress test for MRAM 有权
    MRAM应力测试方法与实现

    公开(公告)号：US07609543B2

    公开(公告)日：2009-10-27

    申请号：US11904434

    申请日：2007-09-27

    申请人： Hsu Kai Yang ,  Lejan Pu ,  Perng-Fei Yuh ,  Po-Kang Wang

    发明人： Hsu Kai Yang ,  Lejan Pu ,  Perng-Fei Yuh ,  Po-Kang Wang

    IPC分类号： G11C11/00

    CPC分类号： G11C11/16 ,  G11C29/06 ,  G11C29/08 ,  G11C29/12005

    摘要： Voltage and current stress for magnetic random access memory (MRAM) cells can weed out potential early failure cells. Method and circuit implementation of such a stress test for a MRAM comprise coupling a stress test circuit to the read bus of the MRAM and stressing the Magnetic Tunnel Junctions (MTJS) by tying them to ground by activating isolation transistors associated with them. Read word lines control which MTJs are stressed Both the method and implementation can be used for any memory cells based on resistance differences, such as Phase RAM or Spin Valve MRAM.

    摘要翻译： 磁性随机存取存储器（MRAM）电池的电压和电流应力可以消除潜在的早期故障电池。 用于MRAM的这种应力测试的方法和电路实现包括将应力测试电路耦合到MRAM的读总线，并通过激活与它们相关联的隔离晶体管将它们绑定到地来强调磁隧道接合点（MTJS）。 读取字线控制哪些MTJ受到压力这两种方法和实现都可以用于基于电阻差异的任何存储单元，如相位RAM或自旋阀MRAM。

    Reference cell scheme for MRAM
    3.
    发明授权
    Reference cell scheme for MRAM 有权
    MRAM参考单元方案

    公开(公告)号：US07499314B2

    公开(公告)日：2009-03-03

    申请号：US12002161

    申请日：2007-12-14

    申请人： Hsu Kai Yang ,  Po-Kang Wang ,  Xizeng Shi

    发明人： Hsu Kai Yang ,  Po-Kang Wang ,  Xizeng Shi

    IPC分类号： G11C11/00

    CPC分类号： G11C7/14 ,  G11C11/16

    摘要： An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines of pairs of the columns together at a location proximally to the sense amplifiers. The MRAM cells of a first of the pair of columns are programmed to a first magneto-resistive state and the MRAM cells of a second of the pair of columns are programmed to a second magneto-resistive state. When one row of data MRAM cells is selected for reading, a row of paired MRAM reference cells are placed in parallel to generate the mid-point reference current for sensing. The MRAM reference sub-array may be programmed electrically or aided by a magnetic field. A method for verifying programming of the MRAM reference sub-array is discussed.

    摘要翻译： MRAM参考单元子阵列提供了一个中点参考电流来检测放大器。 MRAM参考单元子阵列具有以行和列排列的MRAM单元。 位线与子阵列的每一列相关联。 耦合将位列对的位线连接到读出放大器的近端位置。 一对列中的第一列的MRAM单元被编程为第一磁阻状态，并且该对列中的第二对的MRAM单元被编程为第二磁阻状态。 当选择一行数据MRAM单元进行读取时，并行放置一对配对的MRAM参考单元，以生成用于检测的中点参考电流。 MRAM参考子阵列可以被电场编程或由磁场辅助。 讨论了一种用于验证MRAM参考子阵列的编程的方法。

    Spin-torque MRAM: spin-RAM, array
    4.
    发明申请
    Spin-torque MRAM: spin-RAM, array 有权
    旋转力矩MRAM：旋转RAM，阵列

    公开(公告)号：US20080266943A1

    公开(公告)日：2008-10-30

    申请号：US11789324

    申请日：2007-04-24

    申请人： Hsu Kai Yang ,  Po-Kang Wang

    发明人： Hsu Kai Yang ,  Po-Kang Wang

    IPC分类号： G11C11/14

    CPC分类号： G11C11/16

    摘要： A spin-torque MRAM array has MRAM cells arranged in rows and columns. Bit lines are connected to each of the MRAM cells on each column. Source select lines are connected to each MRAM cell of a pair of rows and are oriented orthogonally to the bit lines. Write lines are connected to the gate of the gating MOS transistor of each MRAM cell of the rows. The MRAM cells are written in a two step process with selected MRAM cells written to a first logic level (0) in a first step and selected MRAM cells written to a second logic level (1) in a second step. A second embodiment of the spin-torque MRAM array has the bit lines commonly connected together to receive the data and the source select lines commonly connected together to receive an inverse of the data for writing.

    摘要翻译： 自旋扭矩MRAM阵列具有以行和列排列的MRAM单元。 位线连接到每列上的每个MRAM单元。 源选择线连接到一对行的每个MRAM单元并且与位线正交地定向。 写入线连接到行的每个MRAM单元的选通MOS晶体管的栅极。 MRAM单元以两步过程写入，在第一步骤中将所选MRAM单元写入第一逻辑电平（0），并在第二步骤中将所选择的MRAM单元写入第二逻辑电平（1）。 自旋扭矩MRAM阵列的第二实施例具有通常连接在一起的位线，以接收通常连接在一起的数据和源选择线，以接收用于写入的数据的倒数。

    Reference cell scheme for MRAM
    5.
    发明授权
    Reference cell scheme for MRAM 有权

    公开(公告)号：US07321507B2

    公开(公告)日：2008-01-22

    申请号：US11284299

    申请日：2005-11-21

    申请人： Hsu Kai Yang ,  Po-Kang Wang ,  Xizeng Shi

    发明人： Hsu Kai Yang ,  Po-Kang Wang ,  Xizeng Shi

    IPC分类号： G11C7/00

    CPC分类号： G11C7/14 ,  G11C11/16

    摘要： An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines of pairs of the columns together at a location proximally to the sense amplifiers. The MRAM cells of a first of the pair of columns are programmed to a first magneto-resistive state and the MRAM cells of a second of the pair of columns are programmed to a second magneto-resistive state. When one row of data MRAM cells is selected for reading, a row of paired MRAM reference cells are placed in parallel to generate the mid-point reference current for sensing. The MRAM reference sub-array may be programmed electrically or aided by a magnetic field. A method for verifying programming of the MRAM reference sub-array is discussed.

    Spin-torque MRAM: spin-RAM, array
    6.
    发明授权
    Spin-torque MRAM: spin-RAM, array 有权
    旋转力矩MRAM：旋转RAM，阵列

    公开(公告)号：US07852662B2

    公开(公告)日：2010-12-14

    申请号：US11789324

    申请日：2007-04-24

    申请人： Hsu Kai Yang ,  Po-Kang Wang

    发明人： Hsu Kai Yang ,  Po-Kang Wang

    IPC分类号： G11C11/00

    CPC分类号： G11C11/16

    摘要： A spin-torque MRAM array has MRAM cells arranged in rows and columns. Bit lines are connected to each of the MRAM cells on each column. Source select lines are connected to each MRAM cell of a pair of rows and are oriented orthogonally to the bit lines. Write lines are connected to the gate of the gating MOS transistor of each MRAM cell of the rows. The MRAM cells are written in a two step process with selected MRAM cells written to a first logic level (0) in a first step and selected MRAM cells written to a second logic level (1) in a second step. A second embodiment of the spin-torque MRAM array has the bit lines commonly connected together to receive the data and the source select lines commonly connected together to receive an inverse of the data for writing.

    摘要翻译： 自旋扭矩MRAM阵列具有以行和列排列的MRAM单元。 位线连接到每列上的每个MRAM单元。 源选择线连接到一对行的每个MRAM单元并且与位线正交地定向。 写入线连接到行的每个MRAM单元的选通MOS晶体管的栅极。 MRAM单元以两步过程写入，在第一步骤中将所选MRAM单元写入第一逻辑电平（0），并在第二步骤中将所选择的MRAM单元写入第二逻辑电平（1）。 自旋扭矩MRAM阵列的第二实施例具有通常连接在一起的位线，以接收通常连接在一起的数据和源选择线，以接收用于写入的数据的倒数。

    Configurable MRAM and method of configuration
    8.
    发明授权
    Configurable MRAM and method of configuration 有权
    可配置MRAM和配置方法

    公开(公告)号：US07362644B2

    公开(公告)日：2008-04-22

    申请号：US11313019

    申请日：2005-12-20

    申请人： Hsu Kai Yang ,  Po-Kang Wang ,  Xizeng Shi

    发明人： Hsu Kai Yang ,  Po-Kang Wang ,  Xizeng Shi

    IPC分类号： G11C11/06

    CPC分类号： G11C29/02 ,  G11C7/20 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C29/021 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

    摘要： A configurable MRAM device is achieved. The device comprises a memory array of magnetic memory cells. A first part of the array comprises the memory cells that can be accessed for reading and writing during normal operation. A second part of the array comprises the memory cells that can be read only during a power up initialization. The second part of the array is used to store configuration data for altering the physical operation of the memory array. Programmable current sources and timing delays use the stored configuration data to optimize device performance. A redundant section of memory cells is activated by the configuration data.

    摘要翻译： 实现了可配置的MRAM设备。 该装置包括磁存储单元的存储器阵列。 该阵列的第一部分包括可在正常操作期间被读取和写入的存储器单元。 阵列的第二部分包括只能在上电初始化期间读取的存储器单元。 数组的第二部分用于存储用于更改存储器阵列的物理操作的配置数据。 可编程电流源和定时延迟使用存储的配置数据来优化设备性能。 存储器单元的冗余部分由配置数据激活。

    Highly efficient segmented word line MRAM array
    9.
    发明授权
    Highly efficient segmented word line MRAM array 失效
    高效分段字线MRAM阵列

    公开(公告)号：US07184302B2

    公开(公告)日：2007-02-27

    申请号：US11093613

    申请日：2005-03-30

    申请人： Hsu Kai Yang ,  Po-Kang Wang ,  Xizeng Shi

    发明人： Hsu Kai Yang ,  Po-Kang Wang ,  Xizeng Shi

    IPC分类号： G11C11/00

    CPC分类号： G11C8/14 ,  G11C11/15

    摘要： In an MRAM array based on MTJs, the size of segmented word line select transistors and their associated connections become a significant overhead, especially when the operating point is chosen deep along the hard axis of the asteroid curve. This problem has been overcome by placing the big segmented word line select transistors under the MTJ array and reducing the overall MRAM cell array down to a level comparable to a simple Cross Point MRAM array.

    摘要翻译： 在基于MTJ的MRAM阵列中，分段字线选择晶体管及其相关连接的大小成为显着的开销，特别是当沿着小行星曲线的硬轴选择工作点时。 通过将大分段字线选择晶体管放置在MTJ阵列下并将整个MRAM单元阵列降低到与简单的交叉点MRAM阵列相当的水平，已经克服了这个问题。