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公开(公告)号：US20050152384A1
公开(公告)日：2005-07-14
申请号：US10756438
申请日：2004-01-12
申请人： Huai-Ter Chong , Craig Warner , Richard Adkisson
发明人： Huai-Ter Chong , Craig Warner , Richard Adkisson
IPC分类号： H04L12/56
CPC分类号： H04L47/6265 , H04L47/15 , H04L47/50 , H04L49/30
摘要： Transactions are received through at least two input channels, each transaction comprising one or more data packets. The data packets are placed in a single data queue. When a first transaction received through one input channel comprises more than one data packet, a data packet of a second transaction received through another input channel is permitted to be placed in the single data queue between data packets of the first transaction. A block of space in a data output queue is assigned to each transaction. Each data packet is placed in the block assigned to its transaction.
摘要翻译： 通过至少两个输入通道接收事务，每个事务包括一个或多个数据分组。 数据包被放置在单个数据队列中。 当通过一个输入通道接收到的第一事务包括多于一个数据分组时，允许通过另一个输入通道接收的第二事务的数据分组被放置在第一事务的数据分组之间的单个数据队列中。 数据输出队列中的一个空格块被分配给每个事务。 每个数据包都被放置在分配给它的事务的块中。
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公开(公告)号：US20060026299A1
公开(公告)日：2006-02-02
申请号：US10902341
申请日：2004-07-29
申请人： Gary Gostin , Larry McMahan , Michael Schroeder , Craig Warner , Richard Adkisson , Huai-Ter Chong , David Binford , Mark Shaw , Joe Cowan , Thierry Fevrier , Arad Rostampour
发明人： Gary Gostin , Larry McMahan , Michael Schroeder , Craig Warner , Richard Adkisson , Huai-Ter Chong , David Binford , Mark Shaw , Joe Cowan , Thierry Fevrier , Arad Rostampour
IPC分类号： G06F15/16
CPC分类号： G06F9/5077 , G06F9/544 , G06F15/167
摘要： A computing device having partitions, and a method of communicating between partitions, are disclosed wherein at least one partition comprises: at least one register substantially always accessible to other partitions and capable of defining an address area; at least one address area that may be accessible to other partitions and is capable of being defined by the at least one register; and address areas other than the at least one accessible address area that are not accessible to other partitions. A method of processing interrupts comprising receiving an interrupt, assessing the origin of the interrupt, accepting, rejecting, or further assessing the interrupt, depending on its origin, when further assessing the interrupt, accepting or rejecting the interrupt depending on its contents, and forwarding accepted interrupts but not rejected interrupts to a target processor, and a device carrying out that method are also disclosed.
摘要翻译： 公开了一种具有分区的计算设备和分区之间的通信方法，其中至少一个分区包括：至少一个寄存器，其基本上总是可被其他分区访问并且能够定义地址区域; 至少一个地址区域，其可以由其他分区访问并且能够由所述至少一个寄存器定义; 以及除了其他分区不可访问的至少一个可访问地址区域以外的地址区域。 一种处理中断的方法，包括接收中断，根据其来源评估中断的起始点，接受，拒绝或进一步评估中断，当进一步评估中断时，根据其中的内容接受或拒绝中断，以及转发 接受的中断但不拒绝对目标处理器的中断，并且还公开了执行该方法的设备。
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公开(公告)号：US20050154806A1
公开(公告)日：2005-07-14
申请号：US10756448
申请日：2004-01-12
申请人： Richard Adkisson , Craig Warner , Huai-Ter Chong
发明人： Richard Adkisson , Craig Warner , Huai-Ter Chong
CPC分类号： G06F13/385
摘要： Delivering data from a data input to a data output within a system includes selecting a system performance parameter to be optimized, receiving at the data input a sequence of discrete data words, determining an optimum mode of delivery of the data words to the data output so as to optimize the selected performance parameter, and delivering the data words from the data input to the data output in the determined optimum mode. The optimum mode of delivery may include at least one of an optimum time and sequence of delivery of the data words.
摘要翻译： 将数据从数据输入传送到系统内的数据输出包括选择要优化的系统性能参数，在数据输入处接收一系列离散数据字，确定将数据字传送到数据输出的最佳方式， 以优化所选择的性能参数，并且以确定的最佳模式将数据字从数据输入传送到数据输出。 最佳递送方式可以包括数据字的最佳时间和递送顺序中的至少一个。
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4.发明申请公开(公告)号：US20060063501A1
公开(公告)日：2006-03-23
申请号：US10944524
申请日：2004-09-17
IPC分类号： H04B7/00
CPC分类号： G06F12/0813 , G06F12/0817 , G06F2212/2542
摘要： A method of operating a central cache controller (“CCC”) in a first cell of a multiprocessor system comprising multiple cells each including globally shared memory (“GSM”), wherein the first cell is disposed in a first partition and the CCC is connected to a plurality of CPUs of the first cell. In one embodiment, the method comprises, responsive to a new transaction request from one of the CPUs, logging the transaction in a transaction table; determining whether an identity marker in a timeout map corresponding to a cell to which the transaction was issued is set; and, responsive to the corresponding identity marker in the timeout map being set, immediately returning a special error to the one of the CPUs that requested the transaction.
摘要翻译： 一种在多处理器系统的第一单元中操作中央高速缓存控制器（“CCC”）的方法，包括多个单元，每个单元包括全局共享存储器（“GSM”），其中第一单元被布置在第一分区中并且CCC被连接 到第一小区的多个CPU。 在一个实施例中，该方法包括响应来自CPU之一的新的事务请求，在事务表中记录事务; 确定与发送所述交易的单元对应的超时映射中的身份标识是否被设置; 并且响应于所设置的超时映射中的相应身份标识，立即向请求该事务的一个CPU返回特殊错误。
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公开(公告)号：US20080072110A1
公开(公告)日：2008-03-20
申请号：US11523472
申请日：2006-09-19
IPC分类号： G01R31/28
CPC分类号： G06F11/25
摘要： A system may comprise a condition detection system that includes change circuitry configured to detect a change for at least one predetermined bit of an N-bit bus, where N is a positive integer, and to provide a corresponding change signal indicative of the detected condition. Match circuitry is configured to detect a match condition for up to a selected subset of predetermined bits of the N-bit bus and to provide a corresponding match signal indicative of the detected condition. Selection circuitry is programmable to provide a selected one of the change signal and the match signal as a corresponding output signal.
摘要翻译： 系统可以包括条件检测系统，其包括改变电路，其被配置为检测N位总线的至少一个预定位的改变，其中N是正整数，并且提供指示检测到的条件的对应改变信号。 匹配电路被配置为检测高达N位总线的预定位的选定子集的匹配条件，并提供指示检测到的条件的对应匹配信号。 选择电路是可编程的，以将选择的一个改变信号和匹配信号提供为相应的输出信号。
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公开(公告)号：US20050283677A1
公开(公告)日：2005-12-22
申请号：US11021259
申请日：2004-12-23
申请人： Richard Adkisson , Tyler Johnson
发明人： Richard Adkisson , Tyler Johnson
CPC分类号： G06F11/348 , G06F2201/88
摘要： A circuit for tracking the minimum and maximum duration of an event of interest is described. The circuit is connected to a counter for counting a number of clock cycles that the event of interest is active and comprises logic for detecting deactivation of the event of interest and generating a duration end signal; logic responsive to the duration end signal for comparing a count value with a shadow value; and logic for updating the shadow value based on results of the comparing.
摘要翻译： 描述用于跟踪感兴趣事件的最小和最大持续时间的电路。 电路连接到计数器，用于计数感兴趣事件处于活动状态的多个时钟周期，并且包括用于检测感兴趣事件的去激活并产生持续时间结束信号的逻辑; 响应于持续时间结束信号的逻辑，用于将计数值与阴影值进行比较; 以及基于比较结果来更新阴影值的逻辑。
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公开(公告)号：US20050283669A1
公开(公告)日：2005-12-22
申请号：US11022021
申请日：2004-12-23
申请人： Richard Adkisson , Tyler Johnson
发明人： Richard Adkisson , Tyler Johnson
CPC分类号： G06F11/348 , G06F11/3466 , G06F2201/88
摘要： An edge detect circuit connected to a bus carrying data is described. In one embodiment, the edge detect circuit comprises logic for detecting an edge of a raw increment signal and logic for activating an increment signal upon detection of an edge of the raw increment signal.
摘要翻译： 描述了连接到总线承载数据的边缘检测电路。 在一个实施例中，边缘检测电路包括用于检测原始增量信号的边缘的逻辑和用于在检测到原始增量信号的边缘时激活增量信号的逻辑。
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公开(公告)号：US20050116783A1
公开(公告)日：2005-06-02
申请号：US11034152
申请日：2005-01-12
申请人： Richard Adkisson
发明人： Richard Adkisson
摘要： A phase detector in a programmable clock synchronizer for effectuating data transfer between first circuitry disposed in a first clock domain that is clocked with a first clock signal and second circuitry disposed in a second clock domain that is clocked with a second clock signal. The phase detector includes means for sampling the second clock signal with the first clock signal to generate a sampled clock signal. By tracking movement in a predetermined transition in the sampled clock signal, the phase detector is operable to determine the phase difference between the first and second clock signals.
摘要翻译： 可编程时钟同步器中的相位检测器，用于在布置在与第一时钟信号同步的第一时钟域中的第一电路之间实现数据传输，以及设置在第二时钟域中的第二电路的第二时钟信号。 相位检测器包括用第一时钟信号对第二时钟信号进行采样以产生采样的时钟信号的装置。 通过跟踪在采样的时钟信号中的预定转变中的移动，相位检测器可操作以确定第一和第二时钟信号之间的相位差。
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公开(公告)号：US20050039084A1
公开(公告)日：2005-02-17
申请号：US10945056
申请日：2004-09-20
申请人： Richard Adkisson , Gary Gostin
发明人： Richard Adkisson , Gary Gostin
IPC分类号： H04B1/74
CPC分类号： G06F11/348 , G06F11/364 , G06F2201/88
摘要： A match circuit connected to a bus carrying data is described. In one embodiment, the match circuit includes logic for activating a decoded_match signal, the logic for activating a decoded match signal comprising logic for decoding a sum field comprising a selected portion of the data into a decoded_sum signal, wherein an active bit of the decoded_sum field corresponds to a value of the sum field; and logic for comparing the decoded_sum signal with a mask signal and outputting a binary bit comprising a decoded_match signal indicative of whether the decoded_sum signal and the mask signal match.
摘要翻译： 描述连接到承载数据总线的匹配电路。 在一个实施例中，匹配电路包括用于激活解码匹配信号的逻辑，用于激活解码匹配信号的逻辑，包括逻辑，用于将包括数据的选定部分的和字段解码为解码的信号，其中解码的字段的有效位 对应于和字段的值; 以及用于将decode_sum信号与掩码信号进行比较并输出包括指示解码的信号和掩码信号是否匹配的解码匹配信号的二进制位的逻辑。
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公开(公告)号：US07543173B2
公开(公告)日：2009-06-02
申请号：US11195274
申请日：2005-08-02
申请人： Richard Adkisson
发明人： Richard Adkisson
IPC分类号： G06F1/04
CPC分类号： G06F1/14
摘要： A method of generating a timestamp includes measuring a time period between two events, automatically determining a precision for an indication of the time period, and storing the timestamp. The precision for the indication of the time period is decreased as the time period increases. The timestamp includes an indication of the precision and the indication of the time period, wherein the indication of the time period in the timestamp is stored according to the automatically determined precision.
摘要翻译： 一种产生时间戳的方法包括测量两个事件之间的时间段，自动确定时间段的指示的精度以及存储时间戳。 时间段指示的精度随时间增加而减少。 时间戳包括精度的指示和时间段的指示，其中根据自动确定的精度来存储时间戳中的时间段的指示。
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