公开(公告)号：US06694466B1

公开(公告)日：2004-02-17

申请号：US09428242

申请日：1999-10-27

申请人： Huan-Chih Tsai ,  Kwang-Ting Cheng ,  Sudipta Bhawmik

发明人： Huan-Chih Tsai ,  Kwang-Ting Cheng ,  Sudipta Bhawmik

IPC分类号： G01R3128

CPC分类号： G01R31/318544

摘要： A general test application scheme is proposed for existing scan-based BIST architectures. The objective is to further improve the test quality without inserting additional logic to the Circuit Under Test (CUT). The proposed test scheme divides the entire test process into multiple test sessions. A different number of capture cycles is applied after scanning in a test pattern in each test session to maximize the fault detection for a distinct subset of faults. A procedure is presented to find the optimal number of capture cycles following each scan sequence for every fault. Based on this information, the number of test sessions and the number of capture cycles after each scan sequence are determined to maximize the random testability of the CUT.

摘要翻译： 针对现有的基于扫描的BIST架构提出了一般的测试应用方案。 目的是进一步提高测试质量，而不会向“被测电路”（CUT）插入附加逻辑。 所提出的测试方案将整个测试过程分为多个测试阶段。 在每个测试会话中测试模式扫描后应用不同数量的捕获周期，以最大限度地提高不同故障子集的故障检测。 提出了一个过程，以找出每个故障每个扫描序列之后的最佳捕获周期数。 基于该信息，确定每个扫描序列之后的测试次数和捕获周期数以最大化CUT的随机可测试性。

公开(公告)号：US06463561B1

公开(公告)日：2002-10-08

申请号：US09408371

申请日：1999-09-29

申请人： Sudipta Bhawmik ,  Kwang-Ting Cheng ,  Huan-Chih Tsai

发明人： Sudipta Bhawmik ,  Kwang-Ting Cheng ,  Huan-Chih Tsai

IPC分类号： G01R3128

CPC分类号： G01R31/318544 ,  G01R31/31707 ,  G01R31/318541

摘要： An almost full-scan method and system for detecting faults in circuits can achieve higher fault coverages and significantly shorter test application time as compared with full-scan techniques. A special flip-flop selection of strategy is further described which permits implementation of the almost full-scan BIST method and system.

摘要翻译： 与全扫描技术相比，用于检测电路故障的几乎全扫描方法和系统可以实现更高的故障覆盖率，并显着缩短测试应用时间。 进一步描述了一种特殊的触发器选择策略，其允许实现几乎全扫描的BIST方法和系统。

公开(公告)号：US06256759B1

公开(公告)日：2001-07-03

申请号：US09097488

申请日：1998-06-15

申请人： Sudipta Bhawmik ,  Kwang-Ting Cheng ,  Chih-Jen Lin ,  Huan-Chih Tsai

发明人： Sudipta Bhawmik ,  Kwang-Ting Cheng ,  Chih-Jen Lin ,  Huan-Chih Tsai

IPC分类号： G01R3128

CPC分类号： G01R31/318591 ,  G06F2217/14

摘要： A test point selection method for scan-based built-in self-test (BIST). The method calculates a hybrid cost reduction (HCR) value as an estimated value of the corresponding actual cost reduction for all nodes in a circuit under test. A test point is then selected having a largest HCR. This iterative process continues until the fault coverage of the circuit under test reaches a desired value or the number of test points selected is equal to a maximum number of test points. In an alternative embodiment, the cost reduction factor is calculated for all nodes in the circuit under test, the HCR is calculated for only a selected set of candidates, and the candidate having the largest HCR is selected as the test point. The test point selection method achieves higher fault coverage results and reduces computational processing relative to conventional selection methods.

摘要翻译： 用于基于扫描的内置自检（BIST）的测试点选择方法。 该方法计算混合成本降低（HCR）值作为被测电路中所有节点的相应实际成本降低的估计值。 然后选择具有最大HCR的测试点。 该迭代过程一直持续到被测电路的故障覆盖范围达到所需值或所选择的测试点数等于最大测试点数。 在替代实施例中，针对被测电路中的所有节点计算成本降低因子，仅对选定的候选集合计算HCR，并且选择具有最大HCR的候选者作为测试点。 测试点选择方法相对于常规选择方法实现了更高的故障覆盖结果，并减少了计算处理。

公开(公告)号：US20130197851A1

公开(公告)日：2013-08-01

申请号：US13420742

申请日：2012-03-15

申请人： Sudipta Bhawmik

发明人： Sudipta Bhawmik

IPC分类号： G06F19/00 ,  G01R31/317

CPC分类号： G01R31/318555 ,  G01R31/318513

摘要： Stacked IC devices (or 3D semiconductor devices) have two or more semiconductor devices stacked so they occupy less space than two or more conventionally arranged semiconductor devices. Access to test infrastructures of stacked ICs is provided, regardless of configuration, while using a reduced number of interface pins. A master test controller is provided in a base die and at least one slave test controller is provided in another die. The master test controller is coupled to a test data control (TDC) bus and is configured to broadcast test instructions, test data, and an ID of a slave test controller. The slave test controller is also coupled to the TDC bus, is configured to recognize the broadcast test instructions and test data addressed to the slave test controller, and responds to the instructions when the instructions are addressed to the slave test controller.

摘要翻译： 堆叠的IC器件（或3D半导体器件）具有堆叠的两个或更多个半导体器件，因此它们占据比两个或更多个传统布置的半导体器件更少的空间。 在使用少量接口引脚的情况下，无论配置如何，都提供对堆叠IC的测试基础架构的访问。 主测试控制器设置在基座模具中，并且在另一模具中提供至少一个从测试控制器。 主测试控制器耦合到测试数据控制（TDC）总线，并被配置为广播测试指令，测试数据和从测试控制器的ID。 从测试控制器还耦合到TDC总线，被配置为识别广播测试指令和寻址到从测试控制器的测试数据，并且当指令被寻址到从测试控制器时响应指令。

公开(公告)号：US06463560B1

公开(公告)日：2002-10-08

申请号：US09338338

申请日：1999-06-23

申请人： Sudipta Bhawmik ,  Indradeep Ghosh ,  Niraj Jha

发明人： Sudipta Bhawmik ,  Indradeep Ghosh ,  Niraj Jha

IPC分类号： G01R3187

CPC分类号： G01R31/3187

摘要： A method for testing a controller-data path RTL circuit using a BIST scheme without imposing any major design restrictions on the circuit. A state table is extracted from the controller netlist of the circuit using a state machine extraction program. The untested RTL elements/modules in the circuit are then selected, and the test control and data flow (TCDF) of the circuit are extracted from the controller/data path. Once the TCDF is extracted for the selected RTL elements, a symbolic testability analysis (STA) is performed to obtain test environments for as many untested data path elements as possible. The controller input sequence at the select signals of these test multiplexers needed for the particular test environment is noted and/or stored. A BIST controller is synthesized from the stored input sequences and the circuit is integrated with the BIST components using the thereby determined BIST architecture.

摘要翻译： 一种用于使用BIST方案测试控制器数据路径RTL电路的方法，而不对电路施加任何主要的设计限制。 使用状态机提取程序从控制器网表中提取状态表。 然后选择电路中未经测试的RTL元件/模块，并从控制器/数据通路中提取电路的测试控制和数据流（TCDF）。 一旦为所选择的RTL元素提取TCDF，就执行符号可测试性分析（STA）以获得尽可能多的未经测试的数据路径元素的测试环境。 记录和/或存储特定测试环境所需的这些测试多路复用器的选择信号的控制器输入序列。 从所存储的输入序列合成BIST控制器，并且使用由此确定的BIST架构将电路与BIST组件集成。

公开(公告)号：US6148425A

公开(公告)日：2000-11-14

申请号：US22759

申请日：1998-02-12

申请人： Sudipta Bhawmik ,  Tapan Jyoti Chakraborty ,  Nilanjan Mukherjee

发明人： Sudipta Bhawmik ,  Tapan Jyoti Chakraborty ,  Nilanjan Mukherjee

IPC分类号： G01R31/30 ,  G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/3016 ,  G01R31/31858

摘要： A scan-based BIST architecture for detecting path-delay faults in a sequential circuit converted to a combinational circuit or a less complex sequential circuit including a combinational portion and a plurality of scan flip-flops. The BIST structure includes a test pattern generator for generating two test patterns and a controller for generating a clock signal and an extended scan mode signal which is held high for two clock cycles while the output response of the combinational portion to the first and second test vectors is latched into the scan flip-flops in order to detect a signal transition. The invention is further directed to a method for detection of path-delay faults using this scan-based BIST architecture. To improve the fault coverage for path-delay faults, observation points may be inserted at the inputs of selected scan flip-flops. A predetermined number of scan flip-flops having the highest activation frequency are selected as the observation points.

摘要翻译： 一种基于扫描的BIST架构，用于检测转换到组合电路的顺序电路中的路径延迟故障或包括组合部分和多个扫描触发器的较不复杂的时序电路。 BIST结构包括用于产生两个测试模式的测试模式发生器和用于产生时钟信号的控制器和用于两个时钟周期保持高电平的扩展扫描模式信号，同时组合部分对第一和第二测试向量的输出响应 被锁存到扫描触发器中以便检测信号转换。 本发明还涉及一种使用该基于扫描的BIST架构来检测路径延迟故障的方法。 为了改善路径延迟故障的故障覆盖范围，可以在所选择的扫描触发器的输入端插入观察点。 选择具有最高激活频率的预定数量的扫描触发器作为观察点。

公开(公告)号：US20130185608A1

公开(公告)日：2013-07-18

申请号：US13420099

申请日：2012-03-14

申请人： Sudipta Bhawmik

发明人： Sudipta Bhawmik

IPC分类号： G01R31/3177

CPC分类号： G01R31/318508 ,  G01R31/318513 ,  G01R31/318558

摘要： Stacked integrated circuits (ICs) having a base component and secondary component are tested. The base component has a scan input pad, a scan output pad, a base scan chain, and a base chain access block including a base chain select multiplexor and a base bypass multiplexor. The secondary component has a secondary scan chain and a secondary chain access block including a secondary chain select multiplexor and a secondary bypass multiplexor. The secondary chain select multiplexor is configured to receive input directly from the base component and another component. The base and secondary chain access blocks are configured to selectively access the base scan chain and/or the secondary scan chain.

摘要翻译： 测试具有基本部件和次要部件的堆叠集成电路（IC）。 基部组件具有扫描输入焊盘，扫描输出焊盘，基本扫描链和包括基极链选择多路复用器和基本旁路多路复用器的基本链接接块。 次要组件具有辅助扫描链和辅助链接入块，其包括辅助链选择多路复用器和辅助旁路复用器。 次链选择多路复用器被配置为直接从基本组件和另一组件接收输入。 基本和次级链接访问块被配置为选择性地访问基本扫描链和/或辅助扫描链。

公开(公告)号：US06370664B1

公开(公告)日：2002-04-09

申请号：US09182543

申请日：1998-10-29

申请人： Sudipta Bhawmik

发明人： Sudipta Bhawmik

IPC分类号： G01R3128

CPC分类号： G01R31/318586

摘要： A technique is provided for testing an IC which includes a plurality of flip-flops. The flip-flops are arranged in at least one scan chain. The testing technique of the invention is practiced by selectively partitioning the scan chain into smaller scan chains so that the smaller chains can be simultaneously latched and provide test results. The scan chain is switchable between a partitioned and a non-partitioned configuration, so that either configuration can be selected on demand, thereby allowing both BIST and deterministic testing to be performed efficiently on the same circuit.

摘要翻译： 提供了一种用于测试包括多个触发器的IC的技术。 触发器布置在至少一个扫描链中。 通过将扫描链选择性地划分成更小的扫描链来实现本发明的测试技术，使得较小的链可以同时锁定并提供测试结果。 扫描链可在分区和非分区配置之间切换，从而可以根据需要选择任一配置，从而允许在同一电路上有效执行BIST和确定性测试。

公开(公告)号：US5680543A

公开(公告)日：1997-10-21

申请号：US546055

申请日：1995-10-20

申请人： Sudipta Bhawmik

发明人： Sudipta Bhawmik

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G06F11/27

CPC分类号： G01R31/318552 ,  G01R31/31727

摘要： Built-In Self-Testing of multiple scan chains (12.sub.1 -12.sub.n)can be accomplished by providing separate clock signals (CK.sub.1 -CK.sub.n) that are scheduled by a control circuit (22) so that each chain is clocked at its rated frequency.

摘要翻译： 可以通过提供由控制电路（22）调度的单独的时钟信号（CK1-CKn）来实现多个扫描链（121-12n）的内置自检，使得每个链以其额定频率计时。