公开(公告)号：US12254201B2

公开(公告)日：2025-03-18

申请号：US17994884

申请日：2022-11-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jea Woong Hyun ,  Chun Liu ,  Chaohong Hu ,  Xin Liao

IPC: G06F3/06

Abstract: Write operation and garbage collection methods are provided for a Solid State Drive (SSD) controller of a SSD having Not-AND (NAND) flash memory devices with on-die Static Random Access Memory (SRAM) and NAND flash memory. In the write operation method, a received block of data is stored in on-die SRAM of the NAND flash device, rather than in on-chip SRAM of the controller, prior to programming into NAND flash memory. Until programmed into NAND flash memory, the block of data remains available in the on-die SRAM to fulfill an ‘immediate read’ operation, if received. In the garbage collection method, blocks of data are read from one or more source NAND flash devices and stored in on-die SRAM of a destination NAND flash device until a limit of such blocks has been reached, then the destination NAND flash device programs the blocks from the on-die SRAM into NAND flash memory.

公开(公告)号：US20200183606A1

公开(公告)日：2020-06-11

申请号：US16785967

申请日：2020-02-10

Applicant: Huawei Technologies Co., Ltd.

Inventor： Chaohong Hu

IPC: G06F3/06 ,  G11C16/10

Abstract: A method of performing wear-leveling on a memory implemented by a memory system, comprises determining, by a processor coupled to the receiver and the memory, a circular shifter offset based on a write count of the first portion of the memory, and writing, by the memory, the plurality of user bits and the plurality of error-correcting code (ECC) bits to a plurality of memory cells within a first portion of the memory and a second portion of the memory based on the circular shifter offset.

公开(公告)号：US20230376201A1

公开(公告)日：2023-11-23

申请号：US18365111

申请日：2023-08-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Chaohong Hu ,  Chun Liu ,  Xin Liao

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0644 ,  G06F3/0659 ,  G06F3/0679

Abstract: A method of operating a computing system comprises defining a zoned namespace for non-volatile memory (NVM) of a memory device of the computing system, the zoned namespace including multiple NVM zones of multiple non-overlapping logical block addresses (LBAs) of the NVM, mapping persistence logging (PLOG) identifiers (IDs) to the NVM zones, a PLOG ID identifying a PLOG zone of one or more NVM zones, and performing a PLOG-specific access operation on a PLOG zone of the NVM in response to a PLOG-specific command received from a host device of the computing system.

公开(公告)号：US12277315B2

公开(公告)日：2025-04-15

申请号：US18365111

申请日：2023-08-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Chaohong Hu ,  Chun Liu ,  Xin Liao

IPC: G06F3/06

Abstract: A method of operating a computing system comprises defining a zoned namespace for non-volatile memory (NVM) of a memory device of the computing system, the zoned namespace including multiple NVM zones of multiple non-overlapping logical block addresses (LBAs) of the NVM, mapping persistence logging (PLOG) identifiers (IDs) to the NVM zones, a PLOG ID identifying a PLOG zone of one or more NVM zones, and performing a PLOG-specific access operation on a PLOG zone of the NVM in response to a PLOG-specific command received from a host device of the computing system.

公开(公告)号：US20230152999A1

公开(公告)日：2023-05-18

申请号：US17994884

申请日：2022-11-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jea Woong Hyun ,  Chun Liu ,  Chaohong Hu ,  Xin Liao

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0679 ,  G06F3/0619

Abstract: Write operation and garbage collection methods are provided for a Solid State Drive (SSD) controller of a SSD having Not-AND (NAND) flash memory devices with on-die Static Random Access Memory (SRAM) and NAND flash memory. In the write operation method, a received block of data is stored in on-die SRAM of the NAND flash device, rather than in on-chip SRAM of the controller, prior to programming into NAND flash memory. Until programmed into NAND flash memory, the block of data remains available in the on-die SRAM to fulfill an ‘immediate read’ operation, if received. In the garbage collection method, blocks of data are read from one or more source NAND flash devices and stored in on-die SRAM of a destination NAND flash device until a limit of such blocks has been reached, then the destination NAND flash device programs the blocks from the on-die SRAM into NAND flash memory.

公开(公告)号：US11287999B2

公开(公告)日：2022-03-29

申请号：US16897087

申请日：2020-06-09

Applicant: Huawei Technologies Co., Ltd.

Inventor： Chaohong Hu ,  Zhou Yu

IPC: G06F12/1036 ,  G06F12/109 ,  G06F3/06 ,  G06F9/50 ,  G06Q10/10 ,  G06Q30/02

Abstract: A multi-instance 2-Level-Memory (2LM) architecture manages access by processing instances having different memory usage priorities to memory having different performance and cost levels. The 2LM architecture includes a virtual memory management module that manages access by respective processing instances by creating memory instances based on specified memory usage priority levels and specified virtual memory sizes and defining policies for each usage priority level of the created memory instances. In response to a virtual memory request by a processing instance, the virtual memory management module determines whether a virtual memory size at a designated usage priority level requested by a processing instance can be satisfied by a policy of a created first memory instance and, if not, selects another memory instance that can satisfy the requested virtual memory size at the designated usage priority level and swaps out the first memory instance in favor of the other memory instance.

公开(公告)号：US20200301600A1

公开(公告)日：2020-09-24

申请号：US16897087

申请日：2020-06-09

Applicant: Huawei Technologies Co., Ltd.

Inventor： Chaohong Hu ,  Zhou Yu

IPC: G06F3/06 ,  G06Q10/10 ,  G06Q30/02

Abstract: A multi-instance 2-Level-Memory (2LM) architecture manages access by processing instances having different memory usage priorities to memory having different performance and cost levels. The 2LM architecture includes a virtual memory management module that manages access by respective processing instances by creating memory instances based on specified memory usage priority levels and specified virtual memory sizes and defining policies for each usage priority level of the created memory instances. In response to a virtual memory request by a processing instance, the virtual memory management module determines whether a virtual memory size at a designated usage priority level requested by a processing instance can be satisfied by a policy of a created first memory instance and, if not, selects another memory instance that can satisfy the requested virtual memory size at the designated usage priority level and swaps out the first memory instance in favor of the other memory instance.