公开(公告)号：US20230352552A1

公开(公告)日：2023-11-02

申请号：US18350348

申请日：2023-07-11

Applicant: Huawei Technologies Co., Ltd.

Inventor： Luming Fan ,  Yanxiang Liu ,  Jeffrey Junhao Xu ,  Francis Lionel Benistant ,  Zhaozhao Hou

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/78696 ,  H01L29/66545

Abstract: A memory includes a storage array, at least one source line, at least one word line, and at least one bit line. The storage array includes a plurality of gate-all-around field-effect transistors. The at least one word line is connected to gates of the plurality of gate-all-around field-effect transistors. The at least one source line is connected to sources of the plurality of gate-all-around field-effect transistors. The at least one bit line is connected to drains of the plurality of gate-all-around field-effect transistors. A material of a nanowire of the gate-all-around field-effect transistor is silicon germanium (SiGe). For a next-generation logic process (for example, a GAA process), a storage array including a gate-all-around field-effect transistor manufactured by using a same process as a logic process is used in a memory so that the memory can be compatible with the logic process.