公开(公告)号：US11957062B2

公开(公告)日：2024-04-09

申请号：US17120667

申请日：2020-12-14

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wen Yang ,  Yanxiang Liu

IPC: H01L43/02 ,  H01L27/22 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/80 ,  H10B61/22

Abstract: A memory includes a transistor and a magnetic tunnel junction (MTJ) storage element, a bottom electrode of the MTJ storage element is electrically connected to a drain electrode of the transistor using a conduction structure, wiring layers are disposed between the transistor and the MTJ storage element in the storage area, and a dielectric layer is filled between adjacent wiring layers, the conduction structure includes a first conduction part, and the first conduction part includes a first metal wire, a second metal wire, and a first via hole, the wiring layers comprise a first wiring layer, a second wiring layer, and a third wiring layer, the first via hole penetrates a dielectric layer and the third wiring layer that are located between the first wiring layer and the second wiring layer.

公开(公告)号：US20230352552A1

公开(公告)日：2023-11-02

申请号：US18350348

申请日：2023-07-11

Applicant: Huawei Technologies Co., Ltd.

Inventor： Luming Fan ,  Yanxiang Liu ,  Jeffrey Junhao Xu ,  Francis Lionel Benistant ,  Zhaozhao Hou

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/66439 ,  H01L29/78696 ,  H01L29/66545

Abstract: A memory includes a storage array, at least one source line, at least one word line, and at least one bit line. The storage array includes a plurality of gate-all-around field-effect transistors. The at least one word line is connected to gates of the plurality of gate-all-around field-effect transistors. The at least one source line is connected to sources of the plurality of gate-all-around field-effect transistors. The at least one bit line is connected to drains of the plurality of gate-all-around field-effect transistors. A material of a nanowire of the gate-all-around field-effect transistor is silicon germanium (SiGe). For a next-generation logic process (for example, a GAA process), a storage array including a gate-all-around field-effect transistor manufactured by using a same process as a logic process is used in a memory so that the memory can be compatible with the logic process.

公开(公告)号：US20210249311A1

公开(公告)日：2021-08-12

申请号：US17244410

申请日：2021-04-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sunhom Steve Paak ,  Xiaolong Ma ,  Yanxiang Liu ,  Daxiang Wang ,  Zanfeng Chen ,  Yu Xia ,  Huabin Chen ,  Yongjie Zhou

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: This application provides an integrated circuit device and a preparation method thereof, and relates to the field of semiconductor technologies. An isolation section for suppressing a leakage current path of two adjacent transistors may be formed by using a simple process. The integrated circuit device includes a substrate and a fin protruding from the substrate. The integrated circuit device further includes two adjacent transistors. The two adjacent transistors use two spaced segments on the fin as respective channels of the two adjacent transistors. Apart that is of the fin and that is located between the two spaced segments is processed to obtain an isolation section. The isolation section is used to suppress current transfer between the two channels of the two adjacent transistors.

公开(公告)号：US20210098691A1

公开(公告)日：2021-04-01

申请号：US17120667

申请日：2020-12-14

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wen Yang ,  Yanxiang Liu

IPC: H01L43/02 ,  H01L27/22

Abstract: This application provides a memory including a transistor and an MTJ storage element; a bottom electrode of the MTJ storage element is electrically connected to a drain electrode of the transistor by using a conduction structure; wiring layers are disposed between the transistor and the MTJ storage element in the storage area, and a dielectric layer is filled between adjacent wiring layers; the conduction structure includes a first conduction part, and the first conduction part includes a first metal wire, a second metal wire, and a first via hole; the wiring layers comprise a first wiring layer, a second wiring layer, and a third wiring layer; the first via hole penetrates a dielectric layer and the third wiring layer that are located between the first wiring layer and the second wiring layer.

公开(公告)号：US12148834B2

公开(公告)日：2024-11-19

申请号：US17226563

申请日：2021-04-09

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xinfang Liu ,  Miao Xu ,  Yanxiang Liu

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/49 ,  H01L29/66

Abstract: A field-effect transistor structure includes a semiconductor substrate, a metal gate, a metal trench for source, a metal trench for drain, an etching-stop layer, and a gate contact. The etching-stop layer is overlaid on the metal trench for source and the metal trench for drain. The gate contact is above an active region.

公开(公告)号：US12068202B2

公开(公告)日：2024-08-20

申请号：US17244410

申请日：2021-04-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sunhom Steve Paak ,  Xiaolong Ma ,  Yanxiang Liu ,  Daxiang Wang ,  Zanfeng Chen ,  Yu Xia ,  Huabin Chen ,  Yongjie Zhou

IPC: H01L21/8234 ,  H01L21/02 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823481 ,  H01L21/0259 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: This application provides an integrated circuit device and a preparation method thereof, and relates to the field of semiconductor technologies. An isolation section for suppressing a leakage current path of two adjacent transistors may be formed by using a simple process. The integrated circuit device includes a substrate and a fin protruding from the substrate. The integrated circuit device further includes two adjacent transistors. The two adjacent transistors use two spaced segments on the fin as respective channels of the two adjacent transistors. A part that is of the fin and that is located between the two spaced segments is processed to obtain an isolation section. The isolation section is used to suppress current transfer between the two channels of the two adjacent transistors.

公开(公告)号：US20210257494A1

公开(公告)日：2021-08-19

申请号：US17226563

申请日：2021-04-09

Applicant: Huawei Technologies Co., Ltd.

Inventor： Xinfang Liu ,  Miao Xu ,  Yanxiang Liu

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66

Abstract: A field-effect transistor structure includes a semiconductor substrate, a metal gate, a metal trench for source, a metal trench for drain, an etching-stop layer, and a gate contact, the etching-stop layer is overlaid on the metal trench for source and the metal trench for drain. The gate contact is above an active region.

公开(公告)号：US12073863B2

公开(公告)日：2024-08-27

申请号：US17387588

申请日：2021-07-28

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yue Pan ,  Yanxiang Liu ,  Stephane Badel

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673

Abstract: A memory and an electronic device are provided. The memory includes a storage element (10), a first transistor (21), a second transistor (22), a first bit line (BLA), and a second bit line (BLB). The storage element (10) is coupled to the first bit line (BLA) and the second bit line (BLB) by separately using the first transistor (21) and the second transistor (22), and the first transistor (21) and the second transistor (22) are turned on during a write operation. When the foregoing solution is used, compared with providing a required write current by using one transistor, providing the write current by using the two transistors may enable a smaller transistor to meet a requirement, thereby reducing an area required by the entire memory. In addition, the memory in this application can still support a dual-port feature in a read operation.

公开(公告)号：US20210358531A1

公开(公告)日：2021-11-18

申请号：US17387588

申请日：2021-07-28

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Yue Pan ,  Yanxiang Liu ,  Stephane Badel

IPC: G11C11/16

Abstract: A memory and an electronic device are provided. The memory includes a storage element (10), a first transistor (21), a second transistor (22), a first bit line (BLA), and a second bit line (BLB). The storage element (10) is coupled to the first bit line (BLA) and the second bit line (BLB) by separately using the first transistor (21) and the second transistor (22), and the first transistor (21) and the second transistor (22) are turned on during a write operation. When the foregoing solution is used, compared with providing a required write current by using one transistor, providing the write current by using the two transistors may enable a smaller transistor to meet a requirement, thereby reducing an area required by the entire memory. In addition, the memory in this application can still support a dual-port feature in a read operation.