公开(公告)号：US20130181856A1

公开(公告)日：2013-07-18

申请号：US13728884

申请日：2012-12-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shubao Guo ,  Jun Chen ,  Gong Lei ,  Yongping liu

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M3/50 ,  H03M3/502 ,  H03M7/302

Abstract: An embodiment of the present invention provides a digital-to-analog converter including: a primary modulator; a secondary modulator, connected to the primary modulator; a delay unit, connected to the primary modulator; a subtractor, connected to the delay unit and the secondary modulator separately; a first processing module, configured to perform decoding, dynamic matching, and digital-to-analog conversion in sequence on a B-bit digital signal output by the secondary modulator, so as to obtain a first analog signal; a second processing module, configured to perform decoding, dynamic matching, and digital-to-analog conversion in sequence on an (N−B+1) -bit quantization noise signal output by the subtractor, so as to obtain an analog noise signal; and an adder, connected to the first processing module and the second processing module separately, and configured to add the first analog signal and the analog noise signal, so as to obtain and output a second analog signal.

Abstract translation: 本发明的实施例提供了一种数模转换器，包括：初级调制器; 连接到初级调制器的二次调制器; 延迟单元，连接到初级调制器; 分别连接到延迟单元和次级调制器的减法器; 第一处理模块，被配置为在由二次调制器输出的B位数字信号上依次执行解码，动态匹配和数模转换，以获得第一模拟信号; 第二处理模块，被配置为在由减法器输出的（N-B + 1）位量化噪声信号上依次执行解码，动态匹配和数模转换，以获得模拟噪声信号; 以及加法器，分别连接到第一处理模块和第二处理模块，并且被配置为将第一模拟信号和模拟噪声信号相加，以获得并输出第二模拟信号。