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公开(公告)号：US20240313802A1
公开(公告)日：2024-09-19
申请号：US18606487
申请日：2024-03-15
Applicant: ROHM CO., LTD.
Inventor： Shinji YAMAGAMI
Abstract: An audio D/A converter includes: a first segment D/A converter including N elements; a second segment D/A converter including N elements; a first oversampling filter configured to process a PCM signal; a second oversampling filter configured to process a PCM signal; a first multilevel ΔΣ modulator configured to process an output of the first oversampling filter; a second multilevel ΔΣ modulator configured to process an output of the second oversampling filter; a first switching controller configured to control the first segment D/A converter according to an input to the first switching controller; and a second switching controller configured to control the second segment D/A converter according to an input to the second switching controller.
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公开(公告)号：US11916707B2
公开(公告)日：2024-02-27
申请号：US17701928
申请日：2022-03-23
Inventor： Abhishek Bandyopadhyay , Atsushi Matamura
Abstract: Systems and methods are provided for architectures for an analog feedback class D modulator that increase the power efficiency of the class D modulator. In particular, systems and methods are provided for an analog feedback class D modulator having a digital feed-forward loop. The digital feed-forward loop allows for removal of signal content from an input to an analog-to-digital converter, such that the ADC processes just noise and/or error. Using the techniques discussed herein, the loop filter is low power as it processes error content but not signal content.
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公开(公告)号：US11831306B2
公开(公告)日：2023-11-28
申请号：US17836181
申请日：2022-06-09
Applicant: Infineon Technologies AG
Inventor： Mihail Jefremow , David Zipperstein , Juergen Schaefer , Holger Dienst , Markus Bichl , Ralph Mueller-Eschenbach , Arndt Voigtlaender
Abstract: According to an example, an electronic device includes a component, a supply line providing a supply voltage, a transistor with a control input, a linear first control loop, and a non-linear second control loop. The transistor outputs an output voltage to the component depending on a signal applied to the control input. The linear first control loop includes an ADC to convert an analog output voltage level into a digital measurement signal, a controller to generate a digital control signal for the transistor depending on the digital measurement signal, and a DAC to convert the digital control signal into a first analog control signal. The non-linear second control loop is configured to generate a second analog control signal depending on the analog output voltage level. The second analog control signal is superimposed with the first analog control signal and the combined control signals are fed to the control input of the transistor.
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公开(公告)号：US11757466B2
公开(公告)日：2023-09-12
申请号：US17395902
申请日：2021-08-06
Applicant: Analog Devices, Inc.
Inventor： Abhishek Bandyopadhyay , Preston S. Birdsong , Adam R. Spirer
CPC classification number: H03M3/50 , H03M1/66 , H03M3/39 , H04L25/03006 , H04L25/4917 , H03M1/747 , H04L2025/03363
Abstract: Systems and methods for improving the efficiency of a rotational dynamic element matching (DEM) for Delta Sigma converters. In some implementations, the systems and methods are provided for reducing intersymbol interference (ISI) of a Delta Sigma converter. A delta sigma converter architecture can include multiple I-DACs, and the output from each I-DAC can vary from the other l-DACs. Techniques include decreasing mismatch among multiple l-DACs while improving efficiency of rotational dynamic element matching.
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公开(公告)号：US20180234101A1
公开(公告)日：2018-08-16
申请号：US15435155
申请日：2017-02-16
Applicant: QUALCOMM Incorporated
Inventor： Jingxue Lu , Matthew Sienko
CPC classification number: H03M1/0617 , H03M3/42 , H03M3/432 , H03M3/47 , H03M3/50
Abstract: A system and method for pulse-width modulation (PWM) mismatch shaping. The method includes receiving a multi-bit pulse-code modulated (PCM) signal and generating a voltage ramp signal. The method includes generating a first corrected signal based on a first feedback signal and the multi-bit PCM signal. The method includes generating a first single-bit PWM signal based on the first corrected signal and the voltage ramp signal. The method includes delaying the voltage-ramp signal and generating a second corrected signal based on a second feedback signal and the multi-bit PCM signal. The method includes generating a second single-bit PWM signal based on the second corrected signal and the delayed voltage ramp signal and generating a multi-bit pulse-density modulation (PDM) signal based on the first single-bit PWM signal and the second single-bit PWM signal.
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Patent Agency Ranking
公开(公告)号：US20180139802A1
公开(公告)日：2018-05-17
申请号：US15569802
申请日：2016-03-07
Applicant: NEC Corporation
Inventor： Shinichi HORI , Tomoyuki YAMASE
CPC classification number: H04W88/085 , H03L7/08 , H03L7/0807 , H03M3/02 , H03M3/30 , H03M3/40 , H03M3/458 , H03M3/50 , H04B1/40 , H04B10/25752 , H04B10/40 , H04B2210/006 , H04L27/36 , H04Q11/0067 , H04Q11/0071
Abstract: Provided are a wireless access system provided with a remote unit capable of handling a high-frequency region without being made complicated, and a control method for the same. A wireless access system according to the present invention is provided with: a center unit (1); and a remote unit (3) that converts a baseband signal generated by the center unit (1) into a high-frequency signal and emits the high-frequency signal from an antenna (12). The center unit (1) includes a 1-bit modulator (5) that converts the baseband signal into a 1-bit signal on the basis of a generated clock signal and outputs the 1-bit signal. The remote unit (3) includes: a local generation unit (10) that extracts the clock signal from the 1-bit signal output from the center unit (1), and generates a local signal using the extracted clock signal as a reference signal; a filter (13) that extracts a desired band component from the 1-bit signal; and an up-converter (14) that converts, using the local signal, an output signal of the filter into a high-frequency signal.
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公开(公告)号：US09941897B1
公开(公告)日：2018-04-10
申请号：US15692812
申请日：2017-08-31
Applicant: Analog Devices Global
Inventor： Hongxing Li , Roberto Sergio Matteo Maurino
CPC classification number: H03M1/201 , H03M1/0639 , H03M1/0673 , H03M1/462 , H03M1/66 , H03M1/68 , H03M3/33 , H03M3/42 , H03M3/50
Abstract: A higher accuracy ADC circuit (e.g., in which the number of bits of the ADC circuit is twelve or greater) may need calibration multiple times during its working life to avoid bit weight errors. Described are techniques to address DAC element ratio errors between DAC element clusters in a DAC circuit in order to maintain the linear performance of analog-to-digital converter (ADC) circuits and digital-to-analog converter (DAC) circuits.
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公开(公告)号：US09853658B1
公开(公告)日：2017-12-26
申请号：US15639825
申请日：2017-06-30
Applicant: RICHTEK TECHNOLOGY CORPORATION
Inventor： Ming-Jun Hsiao , Zong-Yi Chen
IPC: H03M3/00
Abstract: A DAC circuit includes: a PWM encoding circuit for converting a digital signal to first and second PWM signals, whereby a combination of the first and second PWM signals becomes a PWM encoded signal of at least 3 levels including a positive, a zero and a negative level, wherein the digital signal represents a number in a numerical range; and a demodulation circuit for generating the analog signal according to the first and second PWM signals. The first and second PWM signals have a minimum duty larger than 0 when the digital signal represents a middle number in the numerical range. The zero level of the combination of the first and second PWM signals has a duty which decreases as a difference between the number represented by the digital signal and the middle number increases.
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公开(公告)号：US09853657B2
公开(公告)日：2017-12-26
申请号：US15489124
申请日：2017-04-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Eeshan Miglani , Karthikeyan Gunasekaran , Santhosh Kumar Gowdhaman , Shagun Dusad
CPC classification number: H03M3/50 , H03M1/00 , H03M1/001 , H03M1/0626 , H03M1/0665 , H03M1/12 , H03M1/747 , H03M3/30 , H03M3/34 , H03M3/422 , H03M3/458 , H03M7/3004
Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.
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公开(公告)号：US20170272045A1
公开(公告)日：2017-09-21
申请号：US15382159
申请日：2016-12-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jasjot Singh CHADHA
CPC classification number: H03F3/2173 , H03F3/183 , H03F2200/03 , H03F2200/331 , H03F2200/351 , H03M3/50 , H04R3/002 , H04R3/04 , H04R29/001
Abstract: A system includes an audio amplifier, a duty cycle detector, a channel equalizer, and a sample-and-hold circuit. The audio amplifier is configured to amplify an analog audio signal to produce an amplified audio signal. The duty cycle detector is configured to generate a saturation detect signal at a first state upon detection that the amplified audio signal produced by the audio amplifier is clipped. The channel equalizer is configured to generate an initial estimate of a speaker terminal voltage. The sample-and-hold circuit is configured to sample and hold the initial estimate of the speaker terminal voltage as a final estimate of the speaker voltage when the saturation detect signal is in the first state.
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