公开(公告)号：US11037615B2

公开(公告)日：2021-06-15

申请号：US16932255

申请日：2020-07-17

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hengchao Xin ,  Jing Xia ,  Yining Li ,  Zhenxi Tu

IPC: G11C11/406

Abstract: A refresh processing method, apparatus, and system, and memory controllers are provided, to improve memory access efficiency. The refresh processing apparatus includes a plurality of memory controllers that are in one-to-one correspondence with a plurality of memory spaces. Any first memory controller in the plurality of memory controllers is configured to: receive N first indication signals and N second indication signals that are output by N memory controllers other than the first memory controller, where N is greater than or equal to 1; and determine a refresh policy of a first memory space based on at least one of the following information: the N first indication signals, the N second indication signals, and refresh indication information of the first memory space.

公开(公告)号：US10114749B2

公开(公告)日：2018-10-30

申请号：US15606428

申请日：2017-05-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zhenxi Tu ,  Jing Xia

IPC: G06F12/0846 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084

Abstract: A cache memory system is provided. The cache memory system includes multiple upper level caches and a current level cache. Each upper level cache includes multiple cache lines. The current level cache includes an exclusive tag random access memory (Exclusive Tag RAM) and an inclusive tag random access memory (Inclusive Tag RAM). The Exclusive Tag RAM is configured to preferentially store an index address of a cache line that is in each upper level cache and whose status is unique dirty (UD). The Inclusive Tag RAM is configured to store an index address of a cache line that is in each upper level cache and whose status is unique clean (UC), shared clean (SC), or shared dirty (SD).

公开(公告)号：US20170262372A1

公开(公告)日：2017-09-14

申请号：US15606428

申请日：2017-05-26

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zhenxi Tu ,  Jing Xia

IPC: G06F12/0846 ,  G06F12/084 ,  G06F12/0831 ,  G06F12/0811

CPC classification number: G06F12/0846 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/283 ,  G06F2212/314

Abstract: A cache memory system is provided. The cache memory system includes multiple upper level caches and a current level cache. Each upper level cache includes multiple cache lines. The current level cache includes an exclusive tag random access memory (Exclusive Tag RAM) and an inclusive tag random access memory (Inclusive Tag RAM). The Exclusive Tag RAM is configured to preferentially store an index address of a cache line that is in each upper level cache and whose status is unique dirty (UD). The Inclusive Tag RAM is configured to store an index address of a cache line that is in each upper level cache and whose status is unique clean (UC), shared clean (SC), or shared dirty (SD).