公开(公告)号：US20250045158A1

公开(公告)日：2025-02-06

申请号：US18920383

申请日：2024-10-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Zhiyong Chen ,  Yining Li ,  Chengchao Wang

IPC: G06F11/10

Abstract: A processing system includes a first memory. The processing system is configured to obtain first data, where the first data is data to be written into the first memory; determine, based on first error distribution area information of at least one memory space included in the first memory, a first arrangement manner of a memory space occupied by a data symbol; determine the first data as M data symbols based on the first arrangement manner of the memory space occupied by the data symbol, where each of the M data symbols includes a plurality of data bits; perform first error correction code encoding on the M data symbols to obtain N first redundant symbols; and write the M data symbols and the N first redundant symbols into the first memory.

公开(公告)号：US20240338328A1

公开(公告)日：2024-10-10

申请号：US18744042

申请日：2024-06-14

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wen Yin ,  Wei Li ,  Yigang Zhou ,  Manbo Wu ,  Xianzhou Lin ,  Chuanwei Wen ,  Ruonan Wang ,  Yining Li

IPC: G06F13/16 ,  G06F13/18 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1668 ,  G06F13/18 ,  G06F13/409 ,  G06F13/4243

Abstract: A data processing system includes a computing subsystem and a memory subsystem. In the computing subsystem, a processor is connected to one end of a high-speed parallel bus via a first bus interface. The processor transmits data to the memory subsystem and receives data transmitted through the high-speed parallel bus. The memory subsystem receives and transmits data to the computing subsystem through the high-speed parallel bus.

公开(公告)号：US11037615B2

公开(公告)日：2021-06-15

申请号：US16932255

申请日：2020-07-17

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hengchao Xin ,  Jing Xia ,  Yining Li ,  Zhenxi Tu

IPC: G11C11/406

Abstract: A refresh processing method, apparatus, and system, and memory controllers are provided, to improve memory access efficiency. The refresh processing apparatus includes a plurality of memory controllers that are in one-to-one correspondence with a plurality of memory spaces. Any first memory controller in the plurality of memory controllers is configured to: receive N first indication signals and N second indication signals that are output by N memory controllers other than the first memory controller, where N is greater than or equal to 1; and determine a refresh policy of a first memory space based on at least one of the following information: the N first indication signals, the N second indication signals, and refresh indication information of the first memory space.