公开(公告)号：US06861696B1

公开(公告)日：2005-03-01

申请号：US10429140

申请日：2003-05-03

申请人： Hyeon-Seag Kim ,  Nian Yang ,  Munseork Choi

发明人： Hyeon-Seag Kim ,  Nian Yang ,  Munseork Choi

IPC分类号： H01L21/28 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7923

摘要： According to one exemplary embodiment, a two-bit memory cell situated over a substrate comprises a tunnel oxide layer situated over the substrate. The two-bit memory cell further comprises a first spacer and a second spacer situated over the tunnel oxide layer, where the first spacer is a first data bit storage location in the two-bit memory cell and the second spacer is a second data bit storage location in the two-bit memory cell. The first spacer and the second spacer may be, for example, silicon nitride or polycrystalline silicon. According to this exemplary embodiment, the two-bit memory cell further comprises an oxide layer situated between the first spacer and the second spacer. The two-bit memory cell further comprises a control gate situated over the oxide layer.

摘要翻译： 根据一个示例性实施例，位于衬底上方的两位存储器单元包括位于衬底上方的隧道氧化物层。 两位存储单元还包括位于隧道氧化物层上的第一间隔物和第二隔离物，其中第一间隔物是两位存储单元中的第一数据位存储位置，第二隔离物是第二数据位存储 位置在两位存储单元中。 第一间隔物和第二间隔物可以是例如氮化硅或多晶硅。 根据该示例性实施例，两比特存储单元还包括位于第一间隔物和第二间隔物之间​​的氧化物层。 两比特存储单元进一步包括位于氧化物层上方的控制栅极。

公开(公告)号：US06693009B1

公开(公告)日：2004-02-17

申请号：US09713390

申请日：2000-11-15

申请人： Hyeon-Seag Kim ,  Unsoon Kim ,  Munseork Choi

发明人： Hyeon-Seag Kim ,  Unsoon Kim ,  Munseork Choi

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： For fabricating a flash memory cell of an electrically programmable memory device on a semiconductor substrate, any region of a stack of a layer of tunnel dielectric material, a layer of floating gate material, a layer of floating dielectric material, and a layer of control gate material, not under a patterning structure, is etched away to form a tunnel dielectric structure comprised of the tunnel dielectric material disposed under the patterning structure, to form a floating gate structure comprised of the floating gate material over the tunnel dielectric structure, to form a floating dielectric structure comprised of the floating dielectric material disposed over the floating gate structure, and to form a control gate structure comprised of the control gate material disposed over the floating dielectric structure. The length of the floating gate structure is trimmed down from a first length of the patterning structure to a second length by etching away a portion of the floating gate material from at least one of a first sidewall and a second sidewall of the floating gate structure. A drain bit line junction of the flash memory cell is formed toward the first sidewall of the floating gate structure, and a source bit line junction of the flash memory cell is formed toward the second sidewall of the floating gate structure. The trim of the length of the floating gate structure minimizes the overlap of the floating gate structure over at least one of the drain bit line junction of the flash memory cell and the source bit line junction of the flash memory cell to minimize leakage of charge from the floating gate structure during programming or erasing of the flash memory cell.

摘要翻译： 为了制造半导体衬底上的电可编程存储器件的闪存单元，隧道介电材料层的堆叠的任何区域，浮栅材料层，浮动电介质材料层和控制栅层 蚀刻掉不在图形结构下面的材料以形成隧道电介质结构，该隧道介电结构由布置在图案化结构下方的隧道介电材料组成，以形成由隧道电介质结构上的浮栅材料构成的浮栅结构，以形成 浮置电介质结构，其包括设置在浮动栅极结构上方的浮置电介质材料，以及形成由设置在浮置电介质结构上的控制栅极材料组成的控制栅极结构。 通过从浮动栅极结构的第一侧壁和第二侧壁中的至少一个蚀刻掉漂浮栅极材料的一部分，浮动栅极结构的长度从图案形成结构的第一长度向下修剪到第二长度。 闪存单元的漏极位线形成朝向浮动栅极结构的第一侧壁，并且闪存单元的源极位置接合部朝向浮动栅极结构的第二侧壁形成。 浮动栅极结构的长度的微调使闪存单元的漏极位线与闪速存储单元的源位线结中的至少一个上的浮置栅极结构的重叠最小化，以最小化从 在闪存单元的编程或擦除期间的浮动栅极结构。