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    BOTTOM GATE THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    BOTTOM GATE THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 失效
    底部薄膜薄膜晶体管及其制造方法

    公开(公告)号：US20100059750A1

    公开(公告)日：2010-03-11

    申请号：US12566106

    申请日：2009-09-24

    申请人： Hyuck LIM ,  Young-soo PARK ,  Wenxu XIANYU ,  Young-kwan CHA

    发明人： Hyuck LIM ,  Young-soo PARK ,  Wenxu XIANYU ,  Young-kwan CHA

    IPC分类号： H01L29/786

    CPC分类号： H01L29/78678 ,  H01L21/268 ,  H01L27/1285 ,  H01L29/66765 ,  H01L29/78609 ,  H01L29/78684 ,  H01L29/78696

    摘要： A method of manufacturing a bottom gate thin film transistor (“TFT”) in which a polycrystalline channel region having a large grain size is formed relatively simply and easily. The method of manufacturing a bottom gate thin film transistor includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the bottom gate electrode, forming an amorphous semiconductor layer, an N-type semiconductor layer and an electrode layer on the gate insulating layer sequentially, etching an electrode region and an N-type semiconductor layer region formed on the bottom gate electrode sequentially to expose an amorphous semiconductor layer region, melting the amorphous semiconductor layer region using a laser annealing method, and crystallizing the melted amorphous semiconductor layer region to form a laterally grown polycrystalline channel region.

    摘要翻译： 相对简单且容易地形成具有大晶粒尺寸的多晶沟道区的底栅薄膜晶体管（“TFT”）的制造方法。 制造底栅极薄膜晶体管的方法包括在衬底上形成底栅电极，在衬底上形成栅极绝缘层以覆盖底栅电极，形成非晶半导体层，N型半导体层和电极 依次在栅极绝缘层上蚀刻形成在底栅电极上的电极区域和N型半导体层区域，以暴露非晶半导体层区域，使用激光退火法熔化非晶半导体层区域，并使 熔融的非晶半导体层区域以形成横向生长的多晶沟道区域。

    BOTTOM GATE THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    BOTTOM GATE THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 审中-公开
    底部薄膜薄膜晶体管及其制造方法

    公开(公告)号：US20070287232A1

    公开(公告)日：2007-12-13

    申请号：US11760043

    申请日：2007-06-08

    申请人： Hyuck LIM ,  Young-soo PARK ,  Wenxu XIANYU ,  Hans S. CHO ,  Huaxiang YIN

    发明人： Hyuck LIM ,  Young-soo PARK ,  Wenxu XIANYU ,  Hans S. CHO ,  Huaxiang YIN

    IPC分类号： H01L21/84 ,  H01L21/00

    CPC分类号： H01L29/66765 ,  H01L21/02532 ,  H01L21/02686 ,  H01L27/1281

    摘要： A method of manufacturing a bottom gate thin film transistor (“TFT”), in which a polycrystalline channel region having a large grain size is formed relatively simply and easily, includes forming a bottom gate electrode on a substrate, forming a gate insulating layer on the substrate to cover the gate electrode, forming an amorphous semiconductor layer on the gate insulating layer, patterning the amorphous semiconductor layer to form an amorphous channel region on the gate electrode, melting the amorphous channel region using a laser annealing method to form a melted amorphous channel region, and crystallizing the melted amorphous channel region to form a laterally grown polycrystalline channel region.

    摘要翻译： 相对简单且容易地形成具有大晶粒尺寸的多晶硅沟道区的底栅薄膜晶体管（“TFT”）的制造方法包括：在基板上形成栅极绝缘层，形成栅极绝缘层 所述基板覆盖所述栅极电极，在所述栅极绝缘层上形成非晶半导体层，图案化所述非晶半导体层以在所述栅电极上形成非晶态沟道区域，使用激光退火方法熔化所述非晶态沟道区域以形成熔融无定形 并使熔融的无定形沟道区域结晶，形成横向生长的多晶沟道区域。

    TRANSISTOR, METHOD OF FABRICATING THE SAME AND ORGANIC LIGHT EMITTING DISPLAY INCLUDING THE TRANSISTOR
    3.
    发明申请
    TRANSISTOR, METHOD OF FABRICATING THE SAME AND ORGANIC LIGHT EMITTING DISPLAY INCLUDING THE TRANSISTOR 有权
    晶体管，其制造方法和包括晶体管的有机发光显示器

    公开(公告)号：US20100178738A1

    公开(公告)日：2010-07-15

    申请号：US12707115

    申请日：2010-02-17

    申请人： Takashi NOGUCHI ,  Jong-man KIM ,  Jang-yeon KWON ,  Kyung-bae PARK ,  Ji-sim JUNG ,  Hyuck LIM

    发明人： Takashi NOGUCHI ,  Jong-man KIM ,  Jang-yeon KWON ,  Kyung-bae PARK ,  Ji-sim JUNG ,  Hyuck LIM

    IPC分类号： H01L21/84

    CPC分类号： H01L29/78645 ,  H01L27/1288 ,  H01L27/3244 ,  H01L29/78624 ,  H01L29/78696

    摘要： A transistor includes; at least two polycrystalline silicon layers disposed substantially parallel to each other, each polycrystalline silicon layer including a channel region and at least two high conductivity regions disposed at opposing sides of the channel region; a gate which corresponds to the channel region of the two polycrystalline silicon layers and which crosses the two polycrystalline silicon layers, and a gate insulating layer interposed between the gate and the two polycrystalline silicon layers, wherein low conductivity regions are disposed adjacent to one edge of the gate and are formed between the channel region and one high conductivity region of each polycrystalline silicon layer.

    摘要翻译： 晶体管包括： 至少两个多晶硅层基本上彼此平行地布置，每个多晶硅层包括沟道区和至少两个设置在沟道区相对侧的高导电性区; 对应于两个多晶硅层的沟道区并与两个多晶硅层交叉的栅极和介于栅极和两个多晶硅层之间的栅极绝缘层，其中低导电性区域邻近 并且形成在每个多晶硅层的沟道区域和一个高导电率区域之间。