Interleaving method for low density parity check encoding
    1.
    发明申请
    Interleaving method for low density parity check encoding 审中-公开
    用于低密度奇偶校验编码的交织方法

    公开(公告)号:US20070186139A1

    公开(公告)日:2007-08-09

    申请号:US10580935

    申请日:2004-11-25

    IPC分类号: H03M13/00

    CPC分类号: H03M13/1102 H03M13/2789

    摘要: An interleaving method for use in a low density parity check (LDPC) encoding process employed by a network across which data is transmitted and/or in a recording/reproducing apparatus when information is stored on a recording medium. The method includes generating more than one code word vector by generating parity information based on a parity check matrix, dividing the generated code word vector into interleaving units, each interleaving unit having a size that is based on bit lengths between 1s included in a row of the parity check matrix, and interleaving the more than one code word vector using the differently sized interleaving units.

    摘要翻译: 一种用于当信息被存储在记录介质上时由数据被发送的网络和/或在记录/再现装置中使用的低密度奇偶校验(LDPC)编码处理中的交织方法。 该方法包括通过基于奇偶校验矩阵产生奇偶校验信息来产生多于一个的代码字向量,将生成的代码字向量划分成交织单元,每个交错单元的大小基于包括在一行 奇偶校验矩阵,并且使用不同大小的交织单元交织多于一个的代码字向量。

    Method of converting parity check matrix for low density parity check coding
    2.
    发明授权
    Method of converting parity check matrix for low density parity check coding 失效
    用于低密度奇偶校验编码的奇偶校验矩阵的转换方法

    公开(公告)号:US07363570B2

    公开(公告)日:2008-04-22

    申请号:US11020017

    申请日:2004-12-23

    IPC分类号: H03M10/00

    CPC分类号: H03M13/1182

    摘要: A method of converting a parity check matrix for low density parity check coding comprising moving rows and columns of the parity check matrix such that the parity check matrix includes a lower triangular submatrix. A calculation load for creating parity information can be reduced by using the converted parity check matrix including the lower triangular submatrix.

    摘要翻译: 一种转换用于低密度奇偶校验编码的奇偶校验矩阵的方法,包括移动奇偶校验矩阵的行和列,使得奇偶校验矩阵包括下三角形子矩阵。 可以通过使用包括下三角子矩阵的转换奇偶校验矩阵来减少用于创建奇偶校验信息的计算负载。

    Method of converting parity check matrix for low density parity check coding
    3.
    发明申请
    Method of converting parity check matrix for low density parity check coding 失效
    用于低密度奇偶校验编码的奇偶校验矩阵的转换方法

    公开(公告)号:US20050235191A1

    公开(公告)日:2005-10-20

    申请号:US11020017

    申请日:2004-12-23

    CPC分类号: H03M13/1182

    摘要: A method of converting a parity check matrix for low density parity check coding comprising moving rows and columns of the parity check matrix such that the parity check matrix includes a lower triangular submatrix. A calculation load for creating parity information can be reduced by using the converted parity check matrix including the lower triangular submatrix.

    摘要翻译: 一种转换用于低密度奇偶校验编码的奇偶校验矩阵的方法,包括移动奇偶校验矩阵的行和列,使得奇偶校验矩阵包括下三角形子矩阵。 可以通过使用包括下三角子矩阵的转换奇偶校验矩阵来减少用于创建奇偶校验信息的计算负载。

    Methods and apparatus for constructing low-density parity check (LDPC) matrix
    4.
    发明授权
    Methods and apparatus for constructing low-density parity check (LDPC) matrix 失效
    用于构建低密度奇偶校验(LDPC)矩阵的方法和装置

    公开(公告)号:US07447972B2

    公开(公告)日:2008-11-04

    申请号:US11081094

    申请日:2005-03-16

    IPC分类号: H03M13/00

    CPC分类号: H03M13/118

    摘要: Methods and apparatus for constructing a parity check matrix for use in a low-density parity check (LDPC) coding scheme are provided. The apparatus includes at least one index generator for generating row indexes of “1”s, which indicate row positions of the “1”s in each column of the parity check matrix, wherein the index generator is implemented by a modular shift register generator that generates a row index of a “1” at each clock.

    摘要翻译: 提供了用于构建用于低密度奇偶校验(LDPC)编码方案的奇偶校验矩阵的方法和装置。 该装置包括至少一个用于产生行索引为“1”的索引生成器,其指示奇偶校验矩阵的每列中的“1”的行位置,其中索引生成器由模块化移位寄存器生成器 在每个时钟产生“1”的行索引。

    Methods and apparatus for constructing low-density parity check (LDPC) matrix
    5.
    发明申请
    Methods and apparatus for constructing low-density parity check (LDPC) matrix 失效
    用于构建低密度奇偶校验(LDPC)矩阵的方法和装置

    公开(公告)号:US20060031745A1

    公开(公告)日:2006-02-09

    申请号:US11081094

    申请日:2005-03-16

    IPC分类号: G06F11/00 H03M13/00

    CPC分类号: H03M13/118

    摘要: Methods and apparatus for constructing a parity check matrix for use in a low-density parity check (LDPC) coding scheme are provided. The apparatus includes at least one index generator for generating row indexes of “1”s, which indicate row positions of the “1”s in each column of the parity check matrix, wherein the index generator is implemented by a modular shift register generator that generates a row index of a “1” at each clock.

    摘要翻译: 提供了用于构建用于低密度奇偶校验(LDPC)编码方案的奇偶校验矩阵的方法和装置。 该装置包括至少一个用于产生行索引为“1”的索引生成器,其指示奇偶校验矩阵的每列中的“1”的行位置,其中索引生成器由模块化移位寄存器生成器 在每个时钟产生“1”的行索引。

    Apparatus and method for constructing low-density parity check matrix
    6.
    发明申请
    Apparatus and method for constructing low-density parity check matrix 审中-公开
    用于构建低密度奇偶校验矩阵的装置和方法

    公开(公告)号:US20060107180A1

    公开(公告)日:2006-05-18

    申请号:US11213994

    申请日:2005-08-30

    IPC分类号: H03M13/00

    CPC分类号: H03M13/118

    摘要: An apparatus and method for constructing a low density parity check matrix. A p-th positive-shift block is generated by shifting all elements of an identity matrix p times to the right; a p-th negative-shift block is generated by shifting all elements of the identity matrix p times to the left; and one or more pairs of different p-th positive- and negative-shift blocks symmetrically arranged in the vertical direction are horizontally arranged.

    摘要翻译: 一种用于构建低密度奇偶校验矩阵的装置和方法。 通过将单位矩阵p的所有元素向右移位来产生第p个正移位块; 通过将单位矩阵p的所有元素向左移位来产生第p个负移位块; 并且在垂直方向上对称布置的一对或多对不同的第p个正负移位块水平布置。

    Analog viterbi decoder
    7.
    发明授权
    Analog viterbi decoder 失效
    模拟维特比解码器

    公开(公告)号:US07751507B2

    公开(公告)日:2010-07-06

    申请号:US11487469

    申请日:2006-07-17

    IPC分类号: H03D1/00

    CPC分类号: H03M13/413 H03M13/6597

    摘要: A circular Viterbi decoder is capable of improving a data decoding speed without being limited by a sampling speed of a sampling and holding circuit. An analog Viterbi decoder includes: a clock divider which generates a plurality of clock signals by dividing a clock frequency of an externally-input clock signal, a plurality of sampling and holding units which sample and hold input analog data according to the clock signals generated from the clock divider, and a multiplexer which sequentially and alternately outputs the analog data sampled and held by the sampling and holding units.

    摘要翻译: 圆形维特比解码器能够提高数据解码速度,而不受采样和保持电路的采样速度的限制。 模拟维特比解码器包括:时钟分频器,其通过除外部输入的时钟信号的时钟频率产生多个时钟信号;多个采样和保持单元,其根据从...生成的时钟信号采样和保持输入模拟数据; 时钟分频器和多路复用器,其顺序并交替地输出由采样和保持单元采样和保持的模拟数据。

    Parity check matrix, method of generating parity check matrix, encoding method and error correction apparatus
    8.
    发明申请
    Parity check matrix, method of generating parity check matrix, encoding method and error correction apparatus 审中-公开
    奇偶校验矩阵,生成奇偶校验矩阵的方法,编码方法和纠错装置

    公开(公告)号:US20070162821A1

    公开(公告)日:2007-07-12

    申请号:US11590820

    申请日:2006-11-01

    IPC分类号: H03M13/00

    CPC分类号: H03M13/116 H03M13/118

    摘要: A parity check matrix making it possible to encode through decoding, a method of generating a parity check matrix, an encoding method and an error correction apparatus including defining an M×N parity check matrix H=[Hm|Hp], and generating an M×M matrix as a sub-matrix Hp wherein all row vectors are linearly independent, a set A of all of the row vectors is a union set of non-empty subsets A1, A2, . . . , Ak (1≦k≦M) that do not include intersection sets with each other, A1 is a set of weight one row vectors, and Ai (2≦i≦k) is a set of row vectors capable of deriving a weight one row vector by a linear combination with row vectors in a union set of the subsets A1, . . . , Ai-1 among the row vectors not included in the union set.

    摘要翻译: 奇偶校验矩阵使得可以通过解码进行编码,产生奇偶校验矩阵的方法,编码方法和纠错装置,包括定义M×N奇偶校验矩阵H = H H 并且生成M×M矩阵作为子矩阵H P p,其中所有行向量是线性独立的,所有行向量的集合A是联合集合 非空子集A 1 ,A 2 ,。 。 。 (1≤k≤M),其中不包括彼此的交集,A 1 <1>是一组权重,一行向量,A < (2 <= i <= k)是能够通过与子集A 1的联合集合中的行向量的线性组合导出权重一行向量的一组行向量, / SUB>,。 。 。 ,不包括在联合集合中的行向量之中的第i-1个

    Viterbi decoder using circulation type decoding units connected in parallel

    公开(公告)号:US20060171490A1

    公开(公告)日:2006-08-03

    申请号:US11342566

    申请日:2006-01-31

    IPC分类号: H03D1/00 H03M13/03

    摘要: An analog Viterbi decoder for decoding an analog signal is provided that includes a plurality of decoding units, provided with a plurality of processing parts each having a plurality of cells arranged to correspond to respective nodes of a trellis diagram, for decoding analog input data using an analog signal processing cell having a circulation type connection structure in which the last processing part is connected to the first processing part; a control unit for performing in parallel a sequential designation of the processing parts with respect to the decoding units; an analog data storage unit including a plurality of capacitors connected in parallel with the processing parts provided in the decoding units; and a first switch unit for storing analog input data in a specific capacitor of the analog data storage units under the control of the control unit. Accordingly, the decoding speed can be remarkably improved.

    METHOD OF CONTROLLING AN OPTICAL DISC DRIVE, AND OPTICAL DISC DRIVE AND OPTICAL INFORMATION WRITING AND/OR READING SYSTEM USING THE METHOD
    10.
    发明申请
    METHOD OF CONTROLLING AN OPTICAL DISC DRIVE, AND OPTICAL DISC DRIVE AND OPTICAL INFORMATION WRITING AND/OR READING SYSTEM USING THE METHOD 有权
    使用该方法控制光盘驱动器的方法和光盘驱动器和光学信息写入和/或读取系统

    公开(公告)号:US20130142027A1

    公开(公告)日:2013-06-06

    申请号:US13674857

    申请日:2012-11-12

    申请人: Hyun-jung Kim

    发明人: Hyun-jung Kim

    IPC分类号: G11B20/00

    摘要: Provided is a method of controlling an optical disc drive, and an optical disc drive using the method. Data that is to be transmitted from a host to the optical disc drive may be encoded. The encoded data may be transmitted to the optical disc drive, and the optical disc drive may decode the encoded data.

    摘要翻译: 提供了一种控制光盘驱动器的方法和使用该方法的光盘驱动器。 可以对从主机传输到光盘驱动器的数据进行编码。 编码数据可以被发送到光盘驱动器,并且光盘驱动器可以解码编码数据。