公开(公告)号：US3918033A

公开(公告)日：1975-11-04

申请号：US52265974

申请日：1974-11-11

Applicant: IBM

Inventor： CASE JERRY R ,  MILLICAN DONALD L ,  NORTON DAVID E

IPC: G11C11/36 ,  G11C11/39 ,  G11C11/41 ,  H03K3/352 ,  G11C11/40

CPC classification number: G11C11/39 ,  H03K3/352

Abstract: A bistable memory cell (stores one binary digit or bit) suitable for semiconductive memories includes a single SCR and a single transistor plus unique interconnections to provide a read-whilewrite array of such cells. The cell topology provides a small cell size with low stand-by power. The SCR provides a memory function, while the single transistor provides an output function. In an alternative embodiment, a second transistor is employed for controlling writing into the cell.

Abstract translation: 适用于半导体存储器的双稳态存储单元（存储一个二进制位或位）包括单个SCR和单个晶体管以及独特的互连，以提供这种单元的读写阵列。 电池拓扑结构提供了具有低备用功率的小单元尺寸。 SCR提供存储功能，而单晶体管提供输出功能。 在替代实施例中，采用第二晶体管来控制对单元的写入。