中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.013 seconds)

    Sensing circuit having regenerative latching circuits responsive to threshold differences in biasing voltages derived from a pair of differentially variable currents
    1.
    发明授权
    Sensing circuit having regenerative latching circuits responsive to threshold differences in biasing voltages derived from a pair of differentially variable currents 失效
    感应电路具有响应于差分电压偏差的差异电压的再生电路电路

    公开(公告)号：US3617770A

    公开(公告)日：1971-11-02

    申请号：US3617770D

    申请日：1969-01-10

    Applicant: IBM

    Inventor： NORTON DAVID E ,  LAKE JOSEPH A JR

    IPC: G11C7/00 ,  G11C7/02 ,  G11C11/06 ,  H03K3/013 ,  H03K3/02 ,  H03K5/20 ,  H03K3/286

    CPC classification number: G11C11/06007

    Abstract: A sensing circuit in which currents in two different paths are differentially varied in response to bipolar input signals. A differential change in the currents sufficient to render the voltage drop across a pair of resistors in either current path approximately equal to the drop across the first one of a like pair of resistors in the other path results in the conduction of the second transistor in an appropriate one of a complementary pair of two-transistor latches to provide an output indication that an input signal at least equal to a predetermined minimum value has been sensed. The voltage drop across the second resistor of each pair establishes an operational threshold which is relatively insensitive to common circuit variations such as in the total current through the two paths, and the latches are regenerative in that conduction by the second transistor in either latch increases the current through the first one of the like pair of resistors to further bias the first transistor thereof into nonconduction.

    SCR memory cell
    4.
    发明授权
    SCR memory cell 失效
    SCR存储单元

    公开(公告)号：US3918033A

    公开(公告)日：1975-11-04

    申请号：US52265974

    申请日：1974-11-11

    Applicant: IBM

    Inventor： CASE JERRY R ,  MILLICAN DONALD L ,  NORTON DAVID E

    IPC: G11C11/36 ,  G11C11/39 ,  G11C11/41 ,  H03K3/352 ,  G11C11/40

    CPC classification number: G11C11/39 ,  H03K3/352

    Abstract: A bistable memory cell (stores one binary digit or bit) suitable for semiconductive memories includes a single SCR and a single transistor plus unique interconnections to provide a read-whilewrite array of such cells. The cell topology provides a small cell size with low stand-by power. The SCR provides a memory function, while the single transistor provides an output function. In an alternative embodiment, a second transistor is employed for controlling writing into the cell.

    Abstract translation: 适用于半导体存储器的双稳态存储单元（存储一个二进制位或位）包括单个SCR和单个晶体管以及独特的互连，以提供这种单元的读写阵列。 电池拓扑结构提供了具有低备用功率的小单元尺寸。 SCR提供存储功能，而单晶体管提供输出功能。 在替代实施例中，采用第二晶体管来控制对单元的写入。

    Gated signal processing circuits for low-level signals
    5.
    发明授权
    Gated signal processing circuits for low-level signals 失效
    用于低电平信号的门控信号处理电路

    公开(公告)号：US3601635A

    公开(公告)日：1971-08-24

    申请号：US3601635D

    申请日：1969-07-10

    Applicant: IBM

    Inventor： NORTON DAVID E

    IPC: G11C7/00 ,  G11C11/06 ,  H03K17/00

    CPC classification number: G11C11/06007

    Abstract: A gated signal processing circuit suitable for use with a magnetic core memory as a sense amplifier. Two symmetrical operational amplifiers receive double-ended input signals respectively from a pair of input terminals and supply them to two high impedance lines. Signal gate and DC restore means receive the amplified signals from the high impedance lines. The latter means includes a pair of like-poled identical windings serially connected across the high impedance lines. A pair of gating transistors operable in the so-called inverted mode are respectively connected across the windings for acting as a gate and enabling DC restoration to the high impedance lines. When current conductive, the inverted-mode, operable transistors clamp the high impedance lines to a predetermined reference potential to place the circuit in an inactive operational state during which time no signals are processed. No base current flows into the windings. When such transistors are switched to a high impedance mode (collector current cutoff), the circuit is placed into an active operational state for processing low-level input signals. An output circuit, connected across the high impedance lines, includes a pair of grounded-base connected, silicon junction transistors having their collectors connected to a single output terminal. The silicon transistors provide a signal threshold such that, when the circuit is in its inactive operational state, noise is not passed to the output terminal. The gate transistors are switched to the high impedance mode for a period of time bracketing the low-level signal processing. Such operation enables DC restoration before and after signal processing.

Patent Agency Ranking