公开(公告)号：US3665210A

公开(公告)日：1972-05-23

申请号：US3665210D

申请日：1970-06-30

Applicant: IBM

Inventor： HO IRVING T ,  HOWELL PETER E ,  JEN TEH-SEN

IPC: G11C19/18 ,  G11C19/28 ,  G11C11/24 ,  G11C11/34 ,  G11C19/00

CPC classification number: G11C19/182 ,  G11C19/28

Abstract: A storage cell suitable for implementation as a monolithic shift register in which a pair of monolithic parasitic capacitors are selectively charged solely in response to periodic non-dc signals to set the digital state of the storage cell. Semiconductor switching means connected between the first and second capacitors is responsive to periodic signals to regenerate the cell for operation in a static mode. Alternatively, a dc circuit prevents loss of cell information during a static mode. The semiconductor switching means is virtually eliminated from the circuit by proper biasing so as to also render the cell operable for use in a dynamic shift register mode.