公开(公告)号：US3697949A

公开(公告)日：1972-10-10

申请号：US3697949D

申请日：1970-12-31

Applicant: IBM

Inventor： CARTER WILLIAM C ,  DUKE KEITH A ,  JESSEP DONALD C JR

IPC: G06F11/10 ,  G06F11/12

CPC classification number: G06F11/1012

Abstract: The present invention relates to a highly-efficient system for performing single-error correction when utilized with a memory system including a memory equipped with error-detection circuitry for use with rotationally-encoded, single-error correction, double-error detection Hamming coded data wherein said memory system circuitry includes means for developing syndrome bits, the patterns of which indicate faulty operation. Hardware is included for first identifying the specific byte which contains the error and still further hardware is provided to locate the particular bit which is erroneous. By efficient use of the rotational characteristic of the present coding scheme, correction is made only when necessary and only that hardware necessary to correct a single byte is provided in the correction circuitry.

Abstract translation: 本发明涉及一种用于执行单一错误校正的高效系统，该系统与存储器系统一起使用，存储器系统包括配备有用于旋转编码的单错误校正，双错误检测汉明编码数据的错误检测电路的存储器 其中所述存储器系统电路包括用于开发校正子位的装置，其模式指示故障操作。 包括硬件，用于首先识别包含错误的特定字节，并且还提供进一步的硬件来定位错误的特定位。 通过有效利用当前编码方案的旋转特性，仅在必要时进行校正，并且仅在校正电路中提供校正单个字节所需的硬件。

公开(公告)号：US3585377A

公开(公告)日：1971-06-15

申请号：US3585377D

申请日：1969-06-16

Applicant: IBM

Inventor： JESSEP DONALD C JR

IPC: G06F11/08 ,  H03M7/00 ,  H03K13/34 ,  H03K19/34

CPC classification number: G06F11/085 ,  H03M7/00

Abstract: A fail-safe decoder utilizing individual fail-safe logic components. The decoder is designed of layers of alternate failure mode logic circuits so that a failure of any of the individual logic elements will always produce an error signal if said failure would cause an output error.

公开(公告)号：US3648239A

公开(公告)日：1972-03-07

申请号：US3648239D

申请日：1970-06-30

Applicant: IBM

Inventor： CARTER WILLIAM C ,  DUKE KEITH A ,  JESSEP DONALD C JR

IPC: G06F11/10 ,  G08C25/00 ,  G06F11/00

CPC classification number: G06F11/1012 ,  G06F11/10

Abstract: An SEC/DED error detection and data translation mechanism is described. By the use of unique circuit design features, the same logical circuitry is capable of automatically taking Hamming encoded data from memory and parity encoding same for transmission elsewhere in the system as well as forming the necessary syndromes for purposes of error detection and correction. The same circuitry is capable of receiving encoded data from elsewhere in the system, first checking for any parity error and, if parity is proper, will generate the necessary Hamming check bits for storing in the memory together with the data information. The disclosed circuitry, by means of the unique partitioning thereof, separates the error detection and correction functions. It also generates parity bits essentially in parallel with error detection after a memory read cycle with the result that the data is propagated through the correction circuitry only when a single data bit error is detected.

Abstract translation: 描述了SEC / DED错误检测和数据转换机制。 通过使用独特的电路设计特征，相同的逻辑电路能够自动地将来自存储器和奇偶校验编码的Hamming编码数据从系统中的其他地方传输，并形成用于错误检测和校正的必要的校验子。 相同的电路能够从系统的其他地方接收编码的数据，首先检查任何奇偶校验错误，并且如果奇偶校验是正确的，则将产生用于与数据信息一起存储在存储器中的必要的汉明校验位。 通过其独特的划分，所公开的电路分离出错误检测和校正功能。 它还在存储器读取周期之后基本上与错误检测并行地生成奇偶校验位，结果是仅当检测到单个数据位错误时，数据被传播通过校正电路。

公开(公告)号：US3705357A

公开(公告)日：1972-12-05

申请号：US3705357D

申请日：1971-03-23

Applicant: IBM

Inventor： CARTER WILLIAM C ,  JESSEP DONALD C JR ,  WADIA ASPI B

IPC: G06F11/16 ,  H03K19/32 ,  H03K19/38

CPC classification number: H03K19/007

Abstract: The present invention relates to a logic circuit for testing the condition of a set of self-testing logic variables. More specifically, it relates to such a logic circuit for forming an Exclusive-Or function on such variables. The circuit has particular utility in high reliability systems for checking the conditions of a plurality of line pairs wherein each line pair constitutes a morphic self-testing variable and wherein the circuit output is itself a morphic self-testing function.

公开(公告)号：US3688265A

公开(公告)日：1972-08-29

申请号：US3688265D

申请日：1971-03-18

Applicant: IBM

Inventor： CARTER WILLIAM C ,  HENLE ROBERT A ,  JESSEP DONALD C JR ,  WADIA ASPI B

IPC: G06F11/10 ,  G06F11/267 ,  G08C25/00 ,  G06F11/00

CPC classification number: G06F11/1044 ,  G06F11/2215

Abstract: A translator for a digital memory system which performs single error correction and double error detection (SEC/DED) upon the stored word in converting it into a parity-encoded form and in addition detects circuit failures in the translator itself. The translator also takes a parity-encoded word, checks the parity encoding, translates the word into an SEC/DED form and writes it into memory. The translator consists of a syndrome generator, a single error corrector, a double error detector, a byte parity encoder, a byte parity checker and a circuit to implement a check on the parity-encoded form of the word which is read. The paritycheck matrix used in formulating the SEC/DED encoded form of the word has the following properties: Property 1: The columns of the parity check matrix are a minimum Hamming distance of 2 apart. Property 2: Each column of the parity check matrix is odd weight. Property 3: If there are r check bits C(j), m bytes with parity bits P(i), and odd parity is used, then

Abstract translation: 一种用于数字存储器系统的翻译器，其对存储的字执行单个纠错和双重错误检测（SEC / DED），将其转换为奇偶校验编码形式，并且还检测翻译器本身中的电路故障。 翻译器还采用奇偶校验编码的字，检查奇偶编码，将该字翻译成SEC / DED格式，并将其写入内存。 翻译器由校正子发生器，单个误差校正器，双重误差检测器，字节奇偶编码器，字节奇偶校验器和用于对读取的字的奇偶校验编码形式进行检查的电路组成。 用于制定SEC / DED编码形式的奇偶校验矩阵具有以下属性：