Abstract:
Each of the pair of transistors of a flip-flop storage cell has its collector connected through a nonlinear impedance means to a low constant current source when the cell is in an inactive condition. The nonlinear impedance means for the conducting transistor maintains the ratio of the load impedance means to the base-emitter impedance of the conducting transistor greater than one to maintain the transistors of the cell in the desired bistable state when the transistors are connected to the low constant current source through the nonlinear impedance means.
Abstract:
A translator for a digital memory system which performs single error correction and double error detection (SEC/DED) upon the stored word in converting it into a parity-encoded form and in addition detects circuit failures in the translator itself. The translator also takes a parity-encoded word, checks the parity encoding, translates the word into an SEC/DED form and writes it into memory. The translator consists of a syndrome generator, a single error corrector, a double error detector, a byte parity encoder, a byte parity checker and a circuit to implement a check on the parity-encoded form of the word which is read. The paritycheck matrix used in formulating the SEC/DED encoded form of the word has the following properties: Property 1: The columns of the parity check matrix are a minimum Hamming distance of 2 apart. Property 2: Each column of the parity check matrix is odd weight. Property 3: If there are r check bits C(j), m bytes with parity bits P(i), and odd parity is used, then