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公开(公告)号：US3909630A
公开(公告)日：1975-09-30
申请号：US43580374
申请日：1974-01-23
Applicant: IBM
Inventor： FIORINO BENJAMIN C , MARINO PETER T
CPC classification number: H04L25/06
Abstract: An H-configured integration circuit includes a pair of squelch transistors forming two legs of the H with a pair of integrating switch transistors forming the other two legs. A pair of capacitors having a common terminal to a reference potential form the crossbar in the H. Rapid integration and differentially balanced squelching is provided for both capacitors. A phase shift measuring circuit shares the squelch reference with the integration circuit such that any variation in the reference on the integrator also adjusts the phase shift measuring circuit. Such circuit differentially compares the integrated values from the integrators with a reference derived from the squelch for indicating phase shift of the input integrated signal with respect to a timing reference.
Abstract translation: H配置的积分电路包括一对形成H的两条支路的静噪晶体管，一对形成另外两条支路的积分开关晶体管。 具有参考电位的公共端的一对电容器形成H中的交叉开关。为两个电容器提供了快速积分和差分平衡镇压。 相移测量电路与积分电路共享静噪参考，使得积分器上的参考的任何变化也调整相移测量电路。 这种电路将来自积分器的积分值与从静噪导出的参考值进行差分比较，用于指示输入积分信号相对于定时参考的相移。
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公开(公告)号：US3909629A
公开(公告)日：1975-09-30
申请号：US51032274
申请日：1974-09-30
Applicant: IBM
Inventor： MARINO PETER T
CPC classification number: G11B20/1419
Abstract: Alternately cycled integrators alternately and successively drive first and second demodulator output circuits to supply data signals to first and second detecting latches, respectively, to convert received periodic digital signals to detected timed data signals. For high-frequency operation, the alternately cycled integrators are squelched in successive alternate time periods after a short predetermined squelch delay. The delay enables reliable sampling of the integrated signal amplitudes.
Abstract translation: 交替循环积分器交替地并且依次驱动第一和第二解调器输出电路，以将数据信号分别提供给第一和第二检测锁存器，以将接收到的周期性数字信号转换成检测到的定时数据信号。 对于高频操作，交替循环积分器在短暂的预定静噪延迟之后的连续交替时间段内被压制。 该延迟使集成信号幅度可靠地采样。
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公开(公告)号：US3877027A
公开(公告)日：1975-04-08
申请号：US43580274
申请日：1974-01-23
Applicant: IBM
Inventor： MARINO PETER T
CPC classification number: G11B20/1419
Abstract: Alternately cycled integrators alternately and successively drive first and second demodulator output circuits to supply data signals to first and second detecting latches, respectively, to convert received periodic digital signals to detected timed data signals. For high-frequency operation, the alternately cycled integrators are squelched in successive alternate time periods after a short predetermined squelch delay. The delay enables reliable sampling of the integrated signal amplitudes. A common data output circuit converts the detected timed data signals to NRZI, NRZ, or other suitable synchronized signal formats. Phase errors are also detected.
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