Abstract:
Data represented in digital signals are detected by integration techniques; each integration occurs over the entire detection or sample period. Recovery of each integration circuit occurs in a subsequent sample period. A pair of integration circuits forming one integrator are provided for each state of the digital signal with the integrators being alternately actuated. In a two-state signal, two integrators are provided; each integrates during a different signal state. To determine data contained in the signal, an amplitude comparison is made between the output of the analog-OR of each integrator of the several signal states. Also disclosed is an extremely sensitive comparator latch which utilizes the high gain of a switching circuit for enhancing amplitude comparison. A clocking system alternately actuating pairs of the integrators is also disclosed.
Abstract:
A data signal read from magnetic tape is converted from an analog signal into a digital signal by hard limiting. This hardlimited data signal is combined with an indication as to whether the amplitude of the digital signal is above a predetermined threshold and then passed to the control unit operating with the tape drive. The control unit, in turn, detects the data, checks for parity error, phase error, and amplitude error and provides control signals back to the tape drive. These control signals are used to change the predetermined threshold used by the tape drive. The predetermined threshold is changed by these control signals in accordance with detection of a history of good data and in accordance with errors in the record block.
Abstract:
An H-configured integration circuit includes a pair of squelch transistors forming two legs of the H with a pair of integrating switch transistors forming the other two legs. A pair of capacitors having a common terminal to a reference potential form the crossbar in the H. Rapid integration and differentially balanced squelching is provided for both capacitors. A phase shift measuring circuit shares the squelch reference with the integration circuit such that any variation in the reference on the integrator also adjusts the phase shift measuring circuit. Such circuit differentially compares the integrated values from the integrators with a reference derived from the squelch for indicating phase shift of the input integrated signal with respect to a timing reference.